R5F21275SDFP#U0 Renesas Electronics America, R5F21275SDFP#U0 Datasheet - Page 317

• Manufacturer Part Number: R5F21275SDFP#U0
• Description: IC R8C/27 MCU FLASH 32LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/27r

Specifications of R5F21275SDFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 25
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• For Use With: R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 16.29
Slave Address Register
IIC bus Transmit Data Register
IIC bus Receive Data Register
IIC bus Shift Register
b7 b6
b7 b6 b5 b4 b3 b2 b1
b7 b6 b5 b4 b3 b2 b1
b7 b6 b5 b4
b5
Sep 26, 2008
b4
b3 b2
b3 b2 b1 b0
Registers SAR, ICDRT, ICDRR, and ICDRS
b1
b0
b0
b0
Store transmit data
When it is detected that the ICDRS register is empty, the stored transmit data item is
transferred to the ICDRS register and data transmission starts.
When the next transmit data item is w ritten to the ICDRT register during transmission of the
data in the ICDRS register, continuous transmit is enabled. When the MLS bit in the ICMR
register is set to 1 (data transferred LSB-first) and after the data is w ritten to the ICDRT
register, the MSB-LSB inverted data is read.
Store receive data
When the ICDRS register receives 1 byte of data, the receive data is transferred to the ICDRR
register and the next receive operation is enabled.
This register is used to transmit and receive data.
The transmit data is transferred from registers ICRDT to the ICDRS and data is transmitted
from the SDA pin w hen transmitting.
After 1 byte of data is received, data is transferred from registers ICDRS to ICDRR w hile
receiving.
Bit Symbol
Symbol
Symbol
Symbol
Symbol
ICDRR
ICDRS
SVA0
SVA1
SVA2
SVA3
SVA4
SVA5
SVA6
ICDRT
SAR
Page 298 of 453
FS
Format select bit
Slave address 6 to 0
Address
Bit Name
00BDh
Address
Address
00BEh
00BFh
Function
Function
Function
0 : I
1 : Clock synchronous serial format
Set an address different from that of the other
slave devices w hich are connected to the I
bus. When the 7 high-order bits of the first
frame transmitted after the starting condition
match bits SVA0 to SVA6 in slave mode of the
I
device.
2
C bus format, the MCU operates as a slave
2
C bus format
16. Clock Synchronous Serial Interface
After Reset
Function
After Reset
After Reset
00h
FFh
FFh
2
C
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
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