R5F21274SNFP#U0 Renesas Electronics America, R5F21274SNFP#U0 Datasheet - Page 336

IC R8C/27 MCU FLASH 32LQFP

R5F21274SNFP#U0

Manufacturer Part Number
R5F21274SNFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet

Specifications of R5F21274SNFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Manufacturer:
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 16.44
16.3.6
Table 16.8
1Tcyc = 1/f1(s)
When setting the I
two cases:
Therefore, the SCL signal is monitored and communication is synchronized bit by bit.
Figure 16.44 shows the Timing of Bit Synchronization Circuit and Table 16.8 lists the Time between Changing
SCL Signal from “L” Output to High-Impedance and Monitoring of SCL Signal.
• If the SCL signal is driven L level by a slave device
• If the rise speed of the SCL signal is reduced by a load (load capacity or pull-up resistor) on the SCL line.
Sep 26, 2008
Bit Synchronization Circuit
CKS3
0
1
Timing of Bit Synchronization Circuit
Monitoring of SCL Signal
Time between Changing SCL Signal from “L” Output to High-Impedance and
ICCR1 Register
SCL monitor timing
Reference clock of
2
C bus interface to master mode, the high-level period may become shorter in the following
Page 317 of 453
Internal SCL
SCL
CKS2
0
1
0
1
VIH
7.5Tcyc
19.5Tcyc
17.5Tcyc
41.5Tcyc
Time for Monitoring SCL
16. Clock Synchronous Serial Interface

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