R5F21274SDFP#U0 Renesas Electronics America, R5F21274SDFP#U0 Datasheet - Page 88

IC R8C/27 MCU FLASH 32LQFP

R5F21274SDFP#U0

Manufacturer Part Number
R5F21274SDFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet

Specifications of R5F21274SDFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Table 7.20
X: 0 or 1
NOTES:
Table 7.21
X: 0 or 1
NOTES:
Table 7.22
X: 0 or 1
NOTES:
Register
Register
Register
Setting
Setting
Setting
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. Set the INT1SEL bit in the PMR register to 0 (P1_5, P1_7).
3. Set the TOPCR bit in the TRAIOC register to 0 in modes except for pulse output mode.
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. Set the SSISEL bit in the PMR register to 1 (P1_6).
3. When the SOOS bit is set to 1 (N-channel open drain output) and BIDE bit is set to 0 (standard mode) in the SSMR2 register,
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. Set the INT1SEL bit in the PMR register to 0 (P1_5, P1_7).
value
value
value
Bit
Bit
Bit
this pin is set to N-channel open drain output.
Sep 26, 2008
PD1_6 CKDIR
PD1
PD1_7
PD1_5
PD1
PD1
X
X
X
0
1
0
Port P1_5/RXD0/(TRAIO)/(INT1)
Port P1_6/CLK0/(SSI)
Port P1_7/TRAIO/INT1
X
0
1
0
X
0
1
0
X
X
X
X
0
1
TIOSEL
TIOSEL
1
0
0
1
0
0
0
0
0
0
Page 69 of 453
0
1
1
0
1
0
1
1
1
1
1
1
TRAIOC
SMD2
TRAIOC
X
0
X
X
X
Other than 001b
U0MR
TOPCR
TOPCR
X
X
X
1
0
0
0
0
0
1
0
0
SMD1
X
X
)
1
0
0
0
0
1
0
0
X
0
X
X
X
(3
(3)
TMOD2
SMD0
TMOD2
X
1
X
X
X
X
0
0
X
0
X
0
0
0
X
X
0
0
0
0
0
0
Other than 000b, 001b
Other than 000b, 001b
Other than 000b, 001b
Other than 000b, 001b
Other than 001b
IICSEL
PMR
TRAMR
TMOD1
X
X
X
X
TRAMR
TMOD1
0
0
X
X
X
0
0
0
0
0
0
X
0
0
X
0
0
0
0
Communication Modes and I/O Pins.)
Clock Synchronous Serial I/O with Chip
SSI output control
TMOD0
TMOD0
Select (Refer to Table 16.4
X
X
X
1
0
0
0
1
1
X
1
0
X
0
0
1
1
Association between
0
0
0
0
1
0
INT1EN
INT1EN
INTEN
INTEN
X
X
X
X
X
0
0
0
0
1
1
1
X
0
0
X
X
0
1
1
1
X
SSI input control
Input port
Output port
RXD0 input
TRAIO input
INT1
TRAIO input/INT1
TRAIO pulse output
Input port
Output port
TRAIO input
INT1
TRAIO input/INT1
TRAIO pulse output
0
0
0
0
0
1
7. Programmable I/O Ports
(2)
(2)
(1)
(1)
(1)
(1)
(1)
Function
Function
Input port
Output port
CLK0 output
CLK0 input
SSI output
SSI input
(1, 2)
(1, 2)
Function
(1, 2)
(1)
(2)
(1)
(3)

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