R5F21274JFP#U0 Renesas Electronics America, R5F21274JFP#U0 Datasheet - Page 237

• Manufacturer Part Number: R5F21274JFP#U0
• Description: MCU FLASH 2K FLASH 16K 32LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/27r

Specifications of R5F21274JFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 14.57
TRCGRD register
TRCGRB register
TRCCR2 register
TRCMR register
The above applies under the following conditions:
• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled).
TRCSR register
TRCSR register
TRCSR register
TRCIOB output
match with the TRCGRB register).
TSTART bit in
Sep 26, 2008
CSEL bit in
IMFC bit in
IMFA bit in
IMFB bit in
Count source
Operating Example of PWM2 Mode (TRCTRG Trigger Input Disabled)
FFFFh
TRC register value
0000h
m
1
0
1
0
1
0
1
0
1
0
n
p
“L” initial output
“H” output at TRCGRC
register compare match
Previous value held if the
TSTRAT bit is set to 0
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p+1
Set to 0 by a program
Return to initial output
if the TSTART bit is
set to 0
n
No change
Set to 0000h
by a program
Transfer from buffer register to general register
m+1
n+1
p+1
Transfer
Set to 1 by
a program
“H” output at TRCGRC register
compare match
Set to 0 by a program
“L” output at TRCGRB
register compare match
n
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
Next data
Set to 0 by a program
TRC register cleared
at TRCGRA register
compare match
TSTART bit
is set to 0
No change
Count stops
because the
CSEL bit is
set to 1
Transfer
14. Timers