R5F21274JFP#U0 Renesas Electronics America, R5F21274JFP#U0 Datasheet - Page 268

MCU FLASH 2K FLASH 16K 32LQFP

R5F21274JFP#U0

Manufacturer Part Number
R5F21274JFP#U0
Description
MCU FLASH 2K FLASH 16K 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet

Specifications of R5F21274JFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F21274JFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Table 15.2
i = 0 or 1
NOTE:
Table 15.3
UiTB
UiRB
UiBRG
UiMR
UiC0
UiC1
TXD0 (P1_4)
RXD0 (P1_5)
CLK0 (P1_6)
TXD1 (either P0_0,
P3_6, or P3_7)
RXD1 (either P3_6,
P3_7, or P4_5)
CLK1 (P0_5)
Table 15.3 lists the I/O Pin Functions in Clock Synchronous Serial I/O Mode. The TXDi (i = 0 or 1) pin outputs
“H” level between the operating mode selection of UARTi and transfer start. (If the NCH bit is set to 1 (N-channel
open-drain output), this pin is in a high-impedance state.)
1. Set bits which are not in this table to 0 when writing to the above registers in clock synchronous
Register
serial I/O mode.
Pin Name
Sep 26, 2008
Registers Used and Settings in Clock Synchronous Serial I/O Mode
I/O Pin Functions in Clock Synchronous Serial I/O Mode
0 to 7
0 to 7
OER
0 to 7
SMD2 to SMD0
CKDIR
CLK1 to CLK0
TXEPT
NCH
CKPOL
UFORM
TE
TI
RE
RI
UiIRS
UiRRM
Page 249 of 453
Bit
Output serial data
Input serial data
Output transfer clock CKDIR bit in U0MR register = 0
Input transfer clock
Output serial data
Input serial data
Output transfer clock CKDIR bit in U1MR register = 0
Input transfer clock
Function
Set data transmission
Data reception can be read
Overrun error flag
Set bit rate
Set to 001b
Select the internal clock or external clock
Select the count source in the UiBRG register
Transmit register empty flag
Select TXDi pin output mode
Select the transfer clock polarity
Select the LSB first or MSB first
Set this bit to 1 to enable transmission/reception
Transmit buffer empty flag
Set this bit to 1 to enable reception
Reception complete flag
Select the UARTi transmit interrupt source
Set this bit to 1 to use continuous receive mode
(Outputs dummy data when performing reception only)
PD1_5 bit in PD1 register = 0
(P1_5 can be used as an input port when performing
transmission only)
CKDIR bit in U0MR register = 1
PD1_6 bit in PD1 register = 0
Set registers PINSR1 and PMR (refer to Figure 15.7
Registers PINSR1 and PMR)
(Outputs dummy data when performing reception only)
Registers PINSR1 and PMR)
Corresponding bit in each port direction register = 0
(Can be used as an input port when performing
transmission only)
PD0_5 bit in PD0 register = 0
CKDIR bit in U1MR register = 1
Set registers PINSR1 and PMR (refer to Figure 15.7
Function
Selection Method
(1)
15. Serial Interface

Related parts for R5F21274JFP#U0