R5F21274JFP#U0 Renesas Electronics America, R5F21274JFP#U0 Datasheet - Page 347

MCU FLASH 2K FLASH 16K 32LQFP

R5F21274JFP#U0

Manufacturer Part Number
R5F21274JFP#U0
Description
MCU FLASH 2K FLASH 16K 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet

Specifications of R5F21274JFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F21274JFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 17.5
Hardware LIN Clear the status flags
Timer RA Set to timer mode
Timer RA Set the pulse output level from low to start
Timer RA Set the INT1/TRAIO pin to P1_5
Timer RA Set the count source (f1, f2, f8, fOCO)
Timer RA Set the Synch Break width
UART0
UART0
UART0
Hardware LIN Set the LIN operation to stop
Hardware LIN Set to master mode
Hardware LIN Set the LIN operation to start
Hardware LIN Set the register to enable interrupts
Sep 26, 2008
Bits TMOD0 to TMOD2 in TRAMR register ← 000b
TEDGSEL bit in TRAIOC register ← 1
TIOSEL bit in TRAIOC register ← 1
Bits TCK0 to TCK2 in TRAMR register
TRAPRE register
TRA register
Set to transmit/receive mode
(Transfer data length: 8 bits, Internal clock, 1 stop bit,
Parity disabled)
U0MR register
Set the BRG count source (f1, f8, f32)
Bits CLK0 to CLK2 in U0C0 register
Set the bit rate
U0BRG register
Example of Header Field Transmission Flowchart (1)
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits B2CLR, B1CLR, B0CLR in LINST register ← 1
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits BCIE, SBIE, SFIE in LINCR register
LINCR register LINE bit ← 0
MST bit in LINCR register ← 1
LINE bit in LINCR register ← 1
Page 328 of 453
A
For the hardware LIN
function, set the TIOSEL bit
in the TRAIOC register to 1.
Set the count source and
registers TRA and TRAPRE
as suitable for the Synch
Break period.
Set the BRG count source
and U0BRG register as
appropriate for the bit rate.
During master mode, the
Synch Field measurement-
completed interrupt cannot be
used.
17. Hardware LIN

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