HD64F3672FPIV Renesas Electronics America, HD64F3672FPIV Datasheet - Page 64
HD64F3672FPIV
Manufacturer Part Number
HD64F3672FPIV
Description
MCU 3/5V 16K I-TEMP PB-FREE 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.HD64F3672FXV.pdf
(334 pages)
Specifications of HD64F3672FPIV
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
26
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 2 CPU
Rev.4.00 Nov. 02, 2005 Page 38 of 304
REJ09B0143-0400
Input/output
Pin state
PCR5
PDR5
RAM0
Input/output
Pin state
PCR5
PDR5
RAM0
MOV.B
MOV.B
MOV.B
BSET
MOV.B
MOV.B
Prior to executing BSET instruction
BSET instruction executed
After executing BSET instruction
#80,
R0L,
R0L,
#0,
@RAM0, R0L
R0L,
P57
Input
Low
level
0
1
1
P57
Input
Low
level
0
1
1
R0L
@RAM0
@PDR5
@PDR5
@RAM0
P56
Input
High
level
0
0
0
P56
Input
High
level
0
0
0
P55
Output
Low
level
1
0
0
P55
Output
Low
level
1
0
0
The PDR5 value (H'80) is written to a work area in
memory (RAM0) as well as to PDR5.
The BSET instruction is executed designating the PDR5
work area (RAM0).
The work area (RAM0) value is written to PDR5.
P54
Output
Low
level
1
0
0
P54
Output
Low
level
1
0
0
P53
Output
Low
level
1
0
0
P53
Output
Low
level
1
0
0
P52
Output
Low
level
1
0
0
P52
Output
Low
level
1
0
0
P51
Output
1
0
0
P51
Output
Low
level
1
0
0
Low
level
P50
Output
Low
level
1
0
0
P50
Output
High
level
1
1
1
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