MC9S08GB60ACFUE Freescale Semiconductor, MC9S08GB60ACFUE Datasheet - Page 123
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MC9S08GB60ACFUE
Manufacturer Part Number
MC9S08GB60ACFUE
Description
IC MCU 60K FLASH 4K RAM 64-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08GT60ACFDER.pdf
(302 pages)
Specifications of MC9S08GB60ACFUE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
56
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
S08GB
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
8
Operating Supply Voltage
0 V to 1.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
M68EVB908GB60E, M68DEMO908GB60E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
For Use With
M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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In this particular case, the MCU has been attached to a PCB and the entire assembly is undergoing final
test with automated test equipment. A separate signal or message is provided to the MCU operating under
user provided software control. The MCU initiates a trim procedure as outlined in
tester supplies a precision reference signal.
If the intended bus frequency is near the maximum allowed for the device, it is recommended to trim using
a reduction divisor (R) twice the final value. Once the trim procedure is complete, the reduction divisor
can be restored. This will prevent accidental overshoot of the maximum clock frequency.
7.5
Refer to the direct-page register summary in
address assignments for all ICG registers. This section refers to registers and control bits only by their
names. A Freescale-provided equate or header file is used to translate these names into the appropriate
absolute addresses.
Freescale Semiconductor
Initial conditions:
1) Clock supplied from ATE has 500 μs duty period
2) ICG configured for internal reference with 4 MHz bus
ICG Registers and Control Bits
INCREASES THE FREQUENCY)
(DECREASING ICGTRM
ICGTRM - 128 / (2**n)
COUNT < EXPECTED = 500
(RUNNING TOO SLOW)
ICGTRM =
n = n + 1
IS n > 8?
MC9S08GB60A Data Sheet, Rev. 2
Figure 7-11. Trim Procedure
(COUNT = # OF BUS CLOCKS / 4)
DECREASES THE FREQUENCY)
NO
START TRIM PROCEDURE
INCOMING CLOCK WIDTH
(INCREASING ICGTRM
ICGTRM = $80, n = 1
ICGTRM + 128 / (2**n)
CASE STATEMENT
Chapter 4,
ICGTRM =
MEASURE
YES
.
COUNT > SZZEXPECTED = 500
(RUNNING TOO FAST)
“Memory” of this data sheet for the absolute
COUNT = EXPECTED = 500
Internal Clock Generator (S08ICGV2)
Figure 7-11
STORE ICGTRM VALUE
IN NON-VOLATILE
CONTINUE
MEMORY
while the
123
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