MC9S08GB60ACFUE Freescale Semiconductor, MC9S08GB60ACFUE Datasheet - Page 168
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MC9S08GB60ACFUE
Manufacturer Part Number
MC9S08GB60ACFUE
Description
IC MCU 60K FLASH 4K RAM 64-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08GT60ACFDER.pdf
(302 pages)
Specifications of MC9S08GB60ACFUE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
56
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
S08GB
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
8
Operating Supply Voltage
0 V to 1.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
M68EVB908GB60E, M68DEMO908GB60E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
For Use With
M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Manufacturer
Quantity
Price
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Timer/PWM (TPM)
10.7.4
TPMxCnSC contains the channel interrupt status flag and control bits that are used to configure the
interrupt enable, channel configuration, and pin function.
168
ELSn[B:A]
Reset
CHnIE
CHnF
MSnB
MSnA
Field
3:2
7
6
5
4
W
R
CHnF
Timer x Channel n Status and Control Register (TPMxCnSC)
Channel n Flag — When channel n is configured for input capture, this flag bit is set when an active edge occurs
on the channel n pin. When channel n is an output compare or edge-aligned PWM channel, CHnF is set when
the value in the TPM counter registers matches the value in the TPM channel n value registers. This flag is
seldom used with center-aligned PWMs because it is set every time the counter matches the channel value
register, which correspond to both edges of the active duty cycle period.
A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF
by reading TPMxCnSC while CHnF is set and then writing a 0 to CHnF. If another interrupt request occurs before
the clearing sequence is complete, the sequence is reset so CHnF would remain set after the clear sequence
was completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost by clearing a
previous CHnF. Reset clears CHnF. Writing a 1 to CHnF has no effect.
0 No input capture or output compare event occurred on channel n
1 Input capture or output compare event occurred on channel n
Channel n Interrupt Enable — This read/write bit enables interrupts from channel n. Reset clears CHnIE.
0 Channel n interrupt requests disabled (use software polling)
1 Channel n interrupt requests enabled
Mode Select B for TPM Channel n — When CPWMS = 0, MSnB = 1 configures TPM channel n for
edge-aligned PWM mode. For a summary of channel mode and setup controls, refer to
Mode Select A for TPM Channel n — When CPWMS = 0 and MSnB = 0, MSnA configures TPM channel n for
input capture mode or output compare mode. Refer to
controls.
Edge/Level Select Bits — Depending on the operating mode for the timer channel as set by
CPWMS:MSnB:MSnA and shown in
input capture event, select the level that will be driven in response to an output compare match, or select the
polarity of the PWM output.
Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated to any timer
channel functions. This function is typically used to temporarily disable an input capture channel or to make the
timer pin available as a general-purpose I/O pin when the associated timer channel is set up as a software timer
that does not require the use of a pin. This is also the setting required for channel 0 when the TPMxCH0 pin is
used as an external clock input.
0
7
Figure 10-10. Timer x Channel n Status and Control Register (TPMxCnSC)
= Unimplemented or Reserved
CHnIE
0
6
Table 10-4. TPMxCnSC Register Field Descriptions
MSnB
MC9S08GB60A Data Sheet, Rev. 2
0
5
Table
MSnA
10-5, these bits select the polarity of the input edge that triggers an
0
4
Description
Table 10-5
ELSnB
3
0
for a summary of channel mode and setup
ELSnA
0
2
Freescale Semiconductor
Table
0
0
1
10-5.
0
0
0