DF2210CUNP24V Renesas Electronics America, DF2210CUNP24V Datasheet - Page 263
DF2210CUNP24V
Manufacturer Part Number
DF2210CUNP24V
Description
MCU 16BIT FLASH 3V 32K 64-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2218UTF24V.pdf
(758 pages)
Specifications of DF2210CUNP24V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Price
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Part Number:
DF2210CUNP24V
Manufacturer:
Renesas Electronics America
Quantity:
135
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7.6
7.6.1
Except for forced termination, the operating (including transfer waiting state) channel setting
should not be changed. The operating channel setting should only be changed when transfer is
disabled. Also, the DMAC register should not be written to in a DMA transfer.
DMAC register reads during operation (including the transfer waiting state) are described below.
1. DMAC control starts one cycle before the bus cycle, with output of the internal address.
DMA Internal
address
DMA register
operation
DMA control
Consequently, MAR is updated in the bus cycle before DMAC transfer.
Figure 7.25 shows an example of the update timing for DMAC registers in dual address
transfer mode.
φ
Usage Notes
DMAC Register Access during Operation
[1]
[2]
[2']
[3]
Note:
Idle
Transfer source address register MAR operation (incremented/decremented/fixed)
Transfer counter ETCR operation (decremented)
Block size counter ETCR operation (decremented in block transfer mode)
Transfer destination address register MAR operation (incremented/decremented/fixed)
Transfer destination address register MAR operation (incremented/decremented/fixed)
Block transfer counter ETCR operation (decremented, in last transfer cycle of
a block in block transfer mode)
Transfer address register MAR restore operation (in block or repeat transfer mode)
Transfer counter ETCR restore (in repeat transfer mode)
Block size counter ETCR restore (in block transfer mode)
The MAR operation is post-incrementing/decrementing of the DMA internal address value.
[1]
Transfer
source
Read
Figure 7.25 DMAC Register Update Timing
[2]
DMA read
destination
DMA transfer cycle
Transfer
Write
DMA write
Idle
[1]
Rev.7.00 Dec. 24, 2008 Page 207 of 698
Transfer
source
Read
[2']
DMA read
DMA last transfer cycle
destination
Transfer
Write
DMA write
[3]
REJ09B0074-0700
Dead
DMA
dead
Idle
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