DF2210CUNP24V Renesas Electronics America, DF2210CUNP24V Datasheet - Page 373
DF2210CUNP24V
Manufacturer Part Number
DF2210CUNP24V
Description
MCU 16BIT FLASH 3V 32K 64-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2218UTF24V.pdf
(758 pages)
Specifications of DF2210CUNP24V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
DF2210CUNP24V
Manufacturer:
Renesas Electronics America
Quantity:
135
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9.5.5
In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When
phase counting mode is set, an external clock is selected as the counter input clock and TCNT
operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1
and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR,
TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used.
This can be used for two-phase encoder pulse input. When overflow occurs while TCNT is
counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down,
the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag
provides an indication of whether TCNT is counting up or down. Table 9.19 shows the
correspondence between external clock pins and channels.
Table 9.19 Phase Counting Mode Clock Input Pins
Example of Phase Counting Mode Setting Procedure: Figure 9.25 shows an example of the
phase counting mode setting procedure.
Channels
When channel 1 is set to phase counting mode
When channel 2 is set to phase counting mode
Phase Counting Mode
Figure 9.25 Example of Phase Counting Mode Setting Procedure
Select phase counting mode
<Phase counting mode>
Phase counting mode
Start count
[1]
[2]
[1]
[2]
Select phase counting mode with bits MD3 to
MD0 in TMDR.
Set the CST bit in TSTR to 1 to start the count
operation.
A-Phase
TCLKC
TCLKA
Rev.7.00 Dec. 24, 2008 Page 317 of 698
External Clock Pins
B-Phase
TCLKB
TCLKD
REJ09B0074-0700
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