DF2210CUNP24V Renesas Electronics America, DF2210CUNP24V Datasheet - Page 434
DF2210CUNP24V
Manufacturer Part Number
DF2210CUNP24V
Description
MCU 16BIT FLASH 3V 32K 64-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2218UTF24V.pdf
(758 pages)
Specifications of DF2210CUNP24V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2210CUNP24V
Manufacturer:
Renesas Electronics America
Quantity:
135
- Current page: 434 of 758
- Download datasheet (5Mb)
Rev.7.00 Dec. 24, 2008 Page 378 of 698
REJ09B0074-0700
Bit
5
4
Bit Name Initial Value R/W
ORER
FER
0
0
R/(W)*
R/(W)*
1
1
Description
Overrun Error
[Setting condition]
•
[Clearing condition]
•
Framing Error
[Setting condition]
•
[Clearing condition]
•
When the next serial reception is completed while
RDRF = 1
The receive data prior to the overrun error is retained
in RDR, and the data received subsequently is lost.
Also, subsequent serial reception cannot be
continued while the ORER flag is set to 1. In clocked
synchronous mode, serial transmission cannot be
continued, either.
When 0 is written to ORER after reading ORER = 1*
The ORER flag is not affected and retains its
previous state when the RE bit in SCR is cleared to
0.
When the stop bit is 0
In 2-stop-bit mode, only the first stop bit is checked
for a value of 0; the second stop bits not checked. If
a framing error occurs, the receive data is transferred
to RDR but the RDRF flag is not set. Also,
subsequent serial reception cannot be continued
while the FER flag is set to 1. In clocked
synchronous mode, serial transmission cannot be
continued, either.
When 0 is written to FER after reading FER = 1*
The FER flag is not affected and retains its previous
state when the RE bit in SCR is cleared to 0.
2
2
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