DF2210CUNP24V Renesas Electronics America, DF2210CUNP24V Datasheet - Page 45
DF2210CUNP24V
Manufacturer Part Number
DF2210CUNP24V
Description
MCU 16BIT FLASH 3V 32K 64-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2218UTF24V.pdf
(758 pages)
Specifications of DF2210CUNP24V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Manufacturer
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Part Number:
DF2210CUNP24V
Manufacturer:
Renesas Electronics America
Quantity:
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Figure 12.35 Clock Halt and Restart Procedure .......................................................................... 437
Figure 12.36 Example of Communication Using the SCI Select Function ................................. 438
Figure 12.37 Example of Communication Using the SCI Select Function ................................. 439
Figure 12.38 Example of Clocked Synchronous Transmission by DMAC ................................. 442
Figure 12.39 Sample Flowchart for Mode Transition during Transmission................................ 444
Figure 12.40 Port Pin State of Asynchronous Transmission Using Internal Clock ..................... 444
Figure 12.41 Port Pin State of Synchronous Transmission Using Internal Clock ....................... 445
Figure 12.42 Sample Flowchart for Mode Transition during Reception ..................................... 446
Figure 12.43 Operation when Switching from SCK Pin Function to Port Pin Function ............. 447
Figure 12.44 Operation when Switching from SCK Pin Function to Port Pin Function
Section 13 Boundary Scan Function
Figure 13.1 Block Diagram of Boundary Scan Function........................................................... 450
Figure 13.2 Boundary Scan Register Configuration.................................................................. 455
Figure 13.3 TAP Controller Status Transition........................................................................... 462
Figure 13.4 Recommended Reset Signal Design....................................................................... 463
Figure 13.5 Serial Data Input/Output ........................................................................................ 463
Section 14 Universal Serial Bus (USB)
Figure 14.1 Block Diagram of USB .......................................................................................... 466
Figure 14.2 USB Initialization................................................................................................... 497
Figure 14.3 USB Cable Connection
Figure 14.4 USB Cable Connection
Figure 14.5 USB Cable Disconnection
Figure 14.6 USB Cable Disconnection
Figure 14.7 Example Flowchart of Suspend and Resume Operations....................................... 502
Figure 14.8 Example Flowchart of Suspend and Resume Interrupt Processing ........................ 503
Figure 14.9 Example Flowchart of Suspend and Remote-Wakeup Operations......................... 504
Figure 14.10 Example Flowchart of Remote-Wakeup Interrupt Processing ............................... 505
Figure 14.11 Control Transfer Stage Configuration .................................................................... 506
Figure 14.12 Setup Stage Operation ............................................................................................ 507
Figure 14.13 Data Stage Operation (Control-In) ......................................................................... 508
Figure 14.14 Data Stage Operation (Control-Out)....................................................................... 509
Figure 14.15 Status Stage Operation (Control-In) ....................................................................... 510
Figure 14.16 Status Stage Operation (Control-Out) .................................................................... 511
Figure 14.17 EP3 Interrupt-In Transfer Operation ...................................................................... 512
(Example of Preventing Low-Level Output).......................................................... 448
(When USB Module Stop or Power-Down Mode Is not Used).............................. 498
(When USB Module Stop or Power-Down Mode Is Used).................................... 499
(When USB Module Stop or Power-Down Mode Is not Used).............................. 500
(When USB Module Stop or Power-Down Mode Is Used).................................... 501
Rev.7.00 Dec. 24, 2008 Page xliii of liv
REJ09B0074-0700
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