DF2210CUNP24V Renesas Electronics America, DF2210CUNP24V Datasheet - Page 658
DF2210CUNP24V
Manufacturer Part Number
DF2210CUNP24V
Description
MCU 16BIT FLASH 3V 32K 64-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2218UTF24V.pdf
(758 pages)
Specifications of DF2210CUNP24V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2210CUNP24V
Manufacturer:
Renesas Electronics America
Quantity:
135
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Table 19.4 External Clock Input Conditions when Duty Adjustment Circuit Is not Used
19.3
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock (φ).
19.4
The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32.
19.5
The bus master clock selection circuit selects the clock supplied to the bus master by setting the
bits SCK2 to SCK0 in SCKCR. The bus master clock can be selected from high-speed mode, or
medium-speed clocks (φ/2, φ/4, φ/8, φ/16, φ/32).
Rev.7.00 Dec. 24, 2008 Page 602 of 698
REJ09B0074-0700
Item
External clock input low pulse width
External clock input high pulse width
External clock rise time
External clock fall time
Duty Adjustment Circuit
Medium-Speed Clock Divider
Bus Master Clock Selection Circuit
EXTAL
t
EXr
Figure 19.5 External Clock Input Timing
Symbol
t
t
t
t
EXL
EXH
EXr
EXf
min
80
80
—
—
t
EXH
max
—
—
15
15
Min
31.25
31.25
—
—
t
EXf
t
EXL
max
—
—
6.25
6.25
min
20.8
20.8
—
—
V
CC
× 0.5
max
—
—
5.25
5.25
Unit
ns
ns
ns
ns
Test
Conditions
Figure 19.5
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