DF2210CUNP24V Renesas Electronics America, DF2210CUNP24V Datasheet - Page 683
DF2210CUNP24V
Manufacturer Part Number
DF2210CUNP24V
Description
MCU 16BIT FLASH 3V 32K 64-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2218UTF24V.pdf
(758 pages)
Specifications of DF2210CUNP24V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2210CUNP24V
Manufacturer:
Renesas Electronics America
Quantity:
135
- Current page: 683 of 758
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20.10
There are three modes, high-speed, medium-speed, and subactive, in which the CPU executes
programs. When a direct transition is made, there is no interruption of program execution when
shifting between high-speed and subactive modes. Direct transitions are enabled by setting the
LPWRCR DTON bit to 1, then executing the SLEEP instruction. After a transition, direct
transition interrupt exception processing starts.
20.10.1 Direct Transitions from High-Speed Mode to Subactive Mode
Execute the SLEEP instruction in high-speed mode when the SBYCR SSBY bit = 1, LPWRCR
LSON bit = 1, and DTON bit = 1, and TSCR_1 PSS bit = 1 to make a transition to subactive
mode.
20.10.2 Direct Transitions from Subactive Mode to High-Speed Mode
Execute the SLEEP instruction in subactive mode when the SBYCR SSBY bit = 1, LPWRCR
LSON bit = 0, and DTON bit = 1, and TSCR_1 PSS bit = 1 to make a direct transition to high-
speed mode after the time set in SBYCR STS2 to STS0 has elapsed.
20.11
Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle,
and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set.
Table 20.4 shows the state of the φ pin in each processing state.
Table 20.4 φ Pin State in Each Processing State
Legend:
×: Don’t care
Register Settings
DDR
0
1
1
Direct Transitions
φ Clock Output Disabling Function
PSTOP
×
0
1
High-Speed Mode,
Medium-Speed Mode,
Subactive Mode
High impedance
φ output
Fixed high
Sleep Mode, Subsleep
Mode
High impedance
φ output
Fixed high
Rev.7.00 Dec. 24, 2008 Page 627 of 698
Software Standby
Mode, Watch Mode,
Direct Transition
High impedance
Fixed high
Fixed high
Hardware Standby
Mode
High impedance
High impedance
High impedance
REJ09B0074-0700
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