MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 590
MCF51EM256CLL
Manufacturer Part Number
MCF51EM256CLL
Description
IC MCU 32BIT 256KB FLASH 100LQFP
Manufacturer
Freescale Semiconductor
Series
MCF51EMr
Datasheets
1.MCF51EM128CLL.pdf
(2 pages)
2.MCF51EM128CLL.pdf
(54 pages)
3.MCF51EM128CLL.pdf
(636 pages)
Specifications of MCF51EM256CLL
Core Processor
Coldfire V1
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SCI, SPI
Peripherals
LCD, LVD, PWM, WDT
Number Of I /o
63
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
MCF51EM
Core
ColdFire V1
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
RS-232, LIN
Maximum Clock Frequency
50 MHz
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
DEMOEM
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Quantity
Price
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Part Number:
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Version 1 ColdFire Debug (CF1_DEBUG)
26.3.10.1 Resulting Set of Possible Trigger Combinations
The resulting set of possible breakpoint trigger combinations consists of the following options where ||
denotes logical OR, && denotes logical AND, and {} denotes an optional additional trigger term:
One-level triggers of the form:
if
if
if
Two-level triggers of the form:
if
if
In these examples, PC_breakpoint is the logical summation of the PBR0/PBMR, PBR1, PBR2, and PBR3
breakpoint registers; Address_breakpoint is a function of ABHR, ABLR, and AATR; Data_breakpoint is
a function of DBR and DBMR. In all cases, the data breakpoints can be included with an address
breakpoint to further qualify a trigger event as an option.
The breakpoint registers can also be used to define the start and stop recording conditions for the PST trace
buffer. For information on this functionality, see
(CSR2)”.
26.3.11 PST Buffer (PSTB)
The PST trace buffer contains 64 six-bit entries, packed consecutively into 12 longword locations. See
Figure 26-15
The write pointer for the trace buffer is available as CSR2[PSTBWA]. Using this pointer, it is possible to
determine the oldest-to-newest entries in the trace buffer.
26-26
(PC_breakpoint)
(PC_breakpoint || Address_breakpoint{&& Data_breakpoint})
(Address_breakpoint {&& Data_breakpoint})
(PC_breakpoint)
then if (Address_breakpoint{&& Data_breakpoint})
(Address_breakpoint {&& Data_breakpoint})
then if (PC_breakpoint)
for an illustration of how the buffer entries are packed.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Table 26-22. Access Size and Operand Data Location
Address[1
00
01
10
11
0x
1x
xx
–
0]
Access Size
Longword
Section 26.3.3, “Configuration/Status Register 2
Word
Word
Byte
Byte
Byte
Byte
Operand Location
D[31
D[23
D[31
D[15
D[15
D[31
D[7
–
–
–
–
–
–
–
24]
16]
0]
16]
8]
0]
0]
Freescale Semiconductor
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