MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 1018

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MC9S12XEQ512CAL

Manufacturer Part Number
MC9S12XEQ512CAL
Description
MCU 16BIT 512K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEQ512CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
91
Eeprom Memory Size
4KB
Ram Memory Size
32KB
Cpu Speed
50MHz
No. Of Timers
3
No. Of Pwm Channels
8
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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27.1
The FTM512K3 module implements the following:
The Flash memory is ideal for single-supply applications allowing for field reprogramming without
requiring external high voltage sources for program or erase operations. The Flash module includes a
memory controller that executes commands to modify Flash memory contents or configure module
resources for emulated EEPROM operation. The user interface to the memory controller consists of the
indexed Flash Common Command Object (FCCOB) register which is written to with the command, global
address, data, and any required command parameters. The memory controller must complete the execution
of a command before the FCCOB register can be written to with a new command.
The RAM and Flash memory may be read as bytes, aligned words, or misaligned words. Read access time
is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. For Flash memory,
an erased bit reads 1 and a programmed bit reads 0.
It is not possible to read from a Flash block while any command is executing on that specific Flash block.
It is possible to read from a Flash block while a command is executing on a different Flash block.
Both P-Flash and D-Flash memories are implemented with Error Correction Codes (ECC) that can resolve
single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation requires that
programming be done on an aligned 8 byte basis (a Flash phrase). Since P-Flash memory is always read
by phrase, only one single bit fault in the phrase containing the byte or word accessed will be corrected.
27.1.1
Buffer RAM — The buffer RAM constitutes the volatile memory store required for EEE. Memory space
in the buffer RAM not required for EEE can be partitioned to provide volatile memory space for
applications.
Freescale Semiconductor
512 Kbytes of P-Flash (Program Flash) memory, consisting of 3 physical Flash blocks, intended
primarily for nonvolatile code storage
32 Kbytes of D-Flash (Data Flash) memory, consisting of 1 physical Flash block, that can be used
as nonvolatile storage to support the built-in hardware scheme for emulated EEPROM, as basic
Flash memory primarily intended for nonvolatile data storage, or as a combination of both
4 Kbytes of buffer RAM, consisting of 1 physical RAM block, that can be used as emulated
EEPROM using a built-in hardware scheme, as basic RAM, or as a combination of both
Introduction
Glossary
A Flash word or phrase must be in the erased state before being
programmed. Cumulative programming of bits within a Flash word or
phrase is not allowed.
MC9S12XE-Family Reference Manual , Rev. 1.23
CAUTION
1018

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