MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 1146

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MC9S12XEQ512CAL

Manufacturer Part Number
MC9S12XEQ512CAL
Description
MCU 16BIT 512K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEQ512CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
91
Eeprom Memory Size
4KB
Ram Memory Size
32KB
Cpu Speed
50MHz
No. Of Timers
3
No. Of Pwm Channels
8
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2)
29.3
This section describes the memory map and registers for the Flash module. Read data from unimplemented
memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space
in the Flash module will be ignored by the Flash module.
29.3.1
The S12X architecture places the P-Flash memory between global addresses 0x70_0000 and 0x7F_FFFF
as shown in
The FPROT register, described in
accidental program or erase. Three separate memory regions, one growing upward from global address
0x7F_8000 in the Flash memory (called the lower region), one growing downward from global address
0x7F_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash
memory, can be activated for protection. The Flash memory addresses covered by these protectable regions
are shown in the P-Flash memory map. The higher address region is mainly targeted to hold the boot loader
code since it covers the vector space. Default protection settings as well as security information that allows
the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in
Table
1146
0x7F_FF00 – 0x7F_FF07
29-3.
Global Address
0x7F_FF0B
0x7F_FF08 –
0x7F_FF0C
0x7F_FF0D
Memory Map and Registers
Module Memory Map
Table
(2)
0x7C_0000 – 0x7F_FFFF
0x7A_0000 – 0x7B_FFFF
0x78_0000 – 0x79_FFFF
0x74_0000 – 0x77_FFFF
0x70_0000 – 0x73_FFFF
2
2
29-2. The P-Flash memory map is shown in
Global Address
(Bytes)
Size
8
4
1
1
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 29-2. P-Flash Memory Addressing
Table 29-3. Flash Configuration Field
Section
Backdoor Comparison Key
Refer to
Section 29.5.1, “Unsecuring the MCU using Backdoor Key
Reserved
P-Flash Protection byte
Refer to
EEE Protection byte
Refer to
29.3.2.9, can be set to protect regions in the Flash memory from
(Bytes)
256 K
128 K
128 K
256 K
256 K
Section 29.4.2.12, “Verify Backdoor Access Key
Section 29.3.2.9, “P-Flash Protection Register (FPROT)”
Section 29.3.2.10, “EEE Protection Register (EPROT)”
Size
P-Flash Block 0
Contains Flash Configuration Field
(see
P-Flash Block 1N
P-Flash Block 1S
P-Flash Block 2
P-Flash Block 3
Table
.
29-3)
Figure
Description
Description
(1)
29-2.
Command,” and
Freescale Semiconductor
Access”

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