MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 1226

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MC9S12XEQ512CAL

Manufacturer Part Number
MC9S12XEQ512CAL
Description
MCU 16BIT 512K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEQ512CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
91
Eeprom Memory Size
4KB
Ram Memory Size
32KB
Cpu Speed
50MHz
No. Of Timers
3
No. Of Pwm Channels
8
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Appendix A Electrical Characteristics
A.3
A.3.1
The time base for all NVM program or erase operations is derived from the oscillator. A minimum
oscillator frequency f
do not have any means to monitor the frequency and will not prevent program or erase operation at
frequencies above or below the specified minimum. When attempting to program or erase the NVM
modules at a lower frequency, a full program or erase transition is not assured.
The program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV
register. The frequency of this clock must be set within the limits specified as f
The minimum program and erase times shown in
maximum f
A.3.1.1
The time it takes to perform a blank check is dependant on the location of the first non-blank word starting
at relative address zero. It takes one bus cycle per phrase to verify plus a setup of the command. Assuming
that no non blank location is found, then the erase verify all blocks is given by.
A.3.1.2
The time it takes to perform a blank check is dependant on the location of the first non-blank word starting
at relative address zero. It takes one bus cycle per phrase to verify plus a setup of the command. Assuming
that no non blank location is found, then the erase verify time for a single 256K NVM array is given by
For a 128K NVM or D-Flash array the erase verify time is given by
A.3.1.3
The maximum time depends on the number of phrases being verified (N
1226
3
t
t
t
t
check
check
check
check
These values include the quantization error which is inherently 1/2 count for any A/D converter.
=
=
=
=
NVM, Flash and Emulated EEPROM
NVMBUS
Timing Parameters
33500
33500
17200
(
752
Erase Verify All Blocks (Blank Check) (FCMD=0x01)
Erase Verify Block (Blank Check) (FCMD=0x02)
Erase Verify P-Flash Section (FCMD=0x03)
+
N
unless otherwise shown. The maximum times are calculated for minimum f
--------------------- -
f
--------------------- -
f
--------------------- -
f
NVMOSC
NVMBUS
NVMBUS
NVMBUS
VP
)
1
1
1
--------------------- -
f
NVMBUS
is required for performing program or erase operations. The NVM modules
MC9S12XE-Family Reference Manual , Rev. 1.23
1
Table A-19
are calculated for maximum f
VP
)
NVMOP
Freescale Semiconductor
.
NVMOP
NVMOP
and

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