MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 198

• Manufacturer Part Number: MC9S12XEQ512CAL
• Description: MCU 16BIT 512K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEQ512CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 32KB
• Cpu Speed: 50MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3 Memory Mapping Control (S12XMMCV4)
Table 3-7
resources (internal) parameters.
198
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
CS3E[1:0]
CS2E[1:0]
CS1E[1:0]
CS0E[1:0]
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
7–6
5–4
3–2
1–0
1. External RPAGE accesses in (NX, EX)
2. When ROMHM is set (see ROMHM in
3. When the internal NVM is enabled (see ROMON in
4. External PPAGE accesses in (NX, EX)
chip memory block.
the CS0 is not asserted in the space occupied by this on-chip memory block.
shows the address boundaries of each chip select and the relationship with the implemented
Chip Select 3 Enables — These bits enable the external chip select CS3 output which is asserted during
accesses to specific external addresses. The associated global address range is shown in
Figure
Chip select 3 is only active if enabled in Normal Expanded mode, Emulation Expanded mode.
The function disabled in all other operating modes.
00
01,10,11 Chip select 3 is enabled
Chip Select 2 Enables — These bits enable the external chip select CS2 output which is asserted during
accesses to specific external addresses. The associated global address range is shown in
Figure
Chip select 2 is only active if enabled in Normal Expanded mode, Emulation Expanded mode.
The function disabled in all other operating modes.
00
01,10,11 Chip select 2 is enabled
Chip Select 1 Enables — These bits enable the external chip select CS1 output which is asserted during
accesses to specific external addresses. The associated global address range is shown in
Figure
Chip select 1 is only active if enabled in Normal Expanded mode, Emulation Expanded mode.
The function disabled in all other operating modes.
00
01,10,11 Chip select 1 is enabled
Chip Select 0 Enables — These bits enable the external chip select CS0 output which is asserted during
accesses to specific external addresses. The associated global address range is shown in
Figure
Chip select 0 is only active if enabled in Normal Expanded mode, Emulation Expanded mode.
The function disabled in all other operating modes.
00
01,10,11 Chip select 0 is enabled
Chip Selects
CS2
CS0
CS3
CS1
3-17.
3-17.
3-17.
3-17.
Chip select 3 is disabled
Chip select 2 is disabled
Chip select 1 is disabled
Chip select 0 is disabled
(2)
(3)
Table 3-7. Global Chip Selects Memory Space
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 3-6. MMCCTL0 Field Descriptions
Bottom Address
0x00_0800
0x14_0000
0x20_0000
0x40_0000
Table
3-16) the CS2 is asserted in the space occupied by this on-
Section 3.3.2.5, “MMC Control Register
Description
0x7F_FFFF minus FLASHSIZE
0x0F_FFFF minus RAMSIZE
Top Address
0x1F_FFFF
0x3F_FFFF
Freescale Semiconductor
(MMCCTL1))
Table 3-7
Table 3-7
Table 3-7
Table 3-7
(1)
(4)
and
and
and
and