MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 222

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MC9S12XEQ512CAL

Manufacturer Part Number
MC9S12XEQ512CAL
Description
MCU 16BIT 512K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEQ512CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
91
Eeprom Memory Size
4KB
Ram Memory Size
32KB
Cpu Speed
50MHz
No. Of Timers
3
No. Of Pwm Channels
8
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 3 Memory Mapping Control (S12XMMCV4)
3.4.4.1
The arbitration scheme allows only one master to be connected to a target at any given time. The following
rules apply when prioritizing accesses from different masters to the same target bus:
3.5
3.5.1
CALL and RTC instructions are uninterruptable CPU instructions that automate page switching in the
program page window. The CALL instruction is similar to the JSR instruction, but the subroutine that is
222
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
CPU always has priority over BDM and XGATE.
XGATE access to PRU registers constitutes a special case. It is always granted and stalls the CPU
for its duration.
XGATE has priority over BDM.
BDM has priority over CPU and XGATE when its access is stalled for more than 128 cycles. In the
later case the suspect master will be stalled after finishing the current operation and the BDM will
gain access to the bus.
In emulation modes all internal accesses are visible on the external bus as well and the external bus
is used during access to the PRU registers.
Initialization/Application Information
EBI
XGATE
CALL and RTC Instructions
XBUS3
Master Bus Prioritization regarding access conflicts on Target Buses
XGATE
XBUS1
FLASH
DBG
FTM
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 3-23. MMC Block Diagram
MMC “Crossbar Switch”
EEE
XBUS0
CPU
S12X0
resources
BDM
BDM
S12X1
XSRAM
XRAM
Freescale Semiconductor
FLEXRAY
IPBI
S12X2
XBUS2

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