MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 320

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MC9S12XEQ512CAL

Manufacturer Part Number
MC9S12XEQ512CAL
Description
MCU 16BIT 512K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEQ512CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
91
Eeprom Memory Size
4KB
Ram Memory Size
32KB
Cpu Speed
50MHz
No. Of Timers
3
No. Of Pwm Channels
8
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 8 S12X Debug (S12XDBGV3) Module
The trigger priorities described in
on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to
final state has priority over all other matches.
8.3.2.7.2
Read: If COMRV[1:0] = 01
Write: If COMRV[1:0] = 01 and S12XDBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the
targeted next state whilst in State2. The matches refer to the match channels of the comparator match
control logic as depicted in
by setting the comparator enable bit in the associated DBGXCTL control register.
320
Address: 0x0027
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
SC[3:0]
SC[3:0]
0000
0001
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
3–0
SC[3:0]
W
R
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
These bits select the targeted next state whilst in State2, based upon the match event.
0
0
7
Debug State Control Register 2 (DBGSCR2)
= Unimplemented or Reserved
Table 8-23. State1 Sequencer Next State Selection (continued)
Match3 triggers to State3....... Match1 triggers to Final State....... Other matches have no effect
Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
Match0 triggers to State2....... Match1 triggers to State3....... Other matches have no effect
Match0 triggers to State2....... Match2 triggers to State3....... Other matches have no effect
Match1 triggers to State2....... Match3 triggers to State3....... Other matches have no effect
Figure 8-10. Debug State Control Register 2 (DBGSCR2)
0
0
6
Table 8-25. State2 —Sequencer Next State Selection
Figure 8-1
MC9S12XE-Family Reference Manual , Rev. 1.23
Match3 has no effect....... All other matches (M0,M1,M2) trigger to State2
Table 8-24. DBGSCR2 Field Descriptions
Table 8-42
Match2 triggers to Final State....... Other matches have no effect
Match2 triggers to State3....... Other matches have no effect
5
0
0
Reserved. (No match triggers state sequencer transition)
Reserved. (No match triggers state sequencer transition)
Reserved. (No match triggers state sequencer transition)
and described in
dictate that in the case of simultaneous matches, the match
Any match triggers to state1
Any match triggers to state3
0
0
4
Description
Description
Section
Description
SC3
0
3
8.3.2.8.1”. Comparators must be enabled
SC2
2
0
Freescale Semiconductor
SC1
0
1
SC0
0
0

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