MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 344

• Manufacturer Part Number: MC9S12XEQ512CAL
• Description: MCU 16BIT 512K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEQ512CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 32KB
• Cpu Speed: 50MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 8 S12X Debug (S12XDBGV3) Module
S12X tagging is disabled when the BDM becomes active. XGATE tagging is possible when the BDM is
active.
8.4.6.1
External tagging using the external TAGHI and TAGLO pins can only be used to tag CPU12X opcodes;
tagging of XGATE code using these pins is not possible. An external tag triggers the state sequencer into
state0 when the tagged opcode reaches the execution stage of the instruction queue.
The pins operate independently, thus the state of one pin does not affect the function of the other. External
tagging is possible in emulation modes only. The presence of logic level 0 on either pin at the rising edge
of the external clock (ECLK) performs the function indicated in the
bytes of an instruction word. If a taghit occurs, a breakpoint can be generated as defined by the DBGBRK
and BDM bits in DBGC1. Each time TAGHI or TAGLO are low on the rising edge of ECLK, the old tag
is replaced by a new one.
8.4.6.2
In emulation modes a low assertion of PE5/TAGLO/MODA in the 7th or 8th bus cycle after reset enables
the unconditional tagging function, allowing immediate tagging via TAGHI/TAGLO with breakpoint to
BDM independent of the ARM, BDM and DBGBRK bits. Conversely these bits are not affected by
unconditional tagging. The unconditional tagging function remains enabled until the next reset. This
function allows an immediate entry to BDM in emulation modes before user code execution. The TAGLO
assertion must be in the 7th or 8th bus cycle following the end of reset, whereby the prior RESET pin
assertion lasts the full 192 bus cycles.
8.4.7
Breakpoints can be generated as follows.
Breakpoints generated by the XGATE module or via the BDM BACKGROUND command have no affect
on the CPU12X in STOP or WAIT mode.
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indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
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Through XGATE software breakpoint requests.
From comparator channel triggers to final state.
Using software to write to the TRIG bit in the DBGC1 register.
From taghits generated using the external TAGHI and TAGLO pins.
Breakpoints
External Tagging using TAGHI and TAGLO
Unconditional Tagging Function
MC9S12XE-Family Reference Manual , Rev. 1.23
TAGHI
1
1
0
0
Table 8-47. Tag Pin Function
TAGLO
1
0
1
0
Both bytes
High byte
Low byte
No tag
Tag
Table
8-47. It is possible to tag both
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