MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 376

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MC9S12XEQ512CAL

Manufacturer Part Number
MC9S12XEQ512CAL
Description
MCU 16BIT 512K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEQ512CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
91
Eeprom Memory Size
4KB
Ram Memory Size
32KB
Cpu Speed
50MHz
No. Of Timers
3
No. Of Pwm Channels
8
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 10 XGATE (S12XGATEV3)
Section for information on how to select priority levels for XGATE threads. Low priority threads (interrupt
levels 1 to 3) can be interrupted by high priority threads (interrupt levels 4 to 7). High priority threads are
not interruptible. The register content of an interrupted thread is maintained and restored by the XGATE
hardware.
To signal the completion of a task the XGATE is able to send interrupts to the S12X_CPU. Each XGATE
channel has its own interrupt vector. Refer to the S12X_INT Section for detailed information.
The XGATE module also provides a set of hardware semaphores which are necessary to ensure data
consistency whenever RAM locations or peripherals are shared with the S12X_CPU.
The following sections describe the components of the XGATE module in further detail.
10.4.1
The RISC core is a 16 bit processor with an instruction set that is well suited for data transfers, bit
manipulations, and simple arithmetic operations (see
It is able to access the MCU’s internal memories and peripherals without blocking these resources from
the S12X_CPU
will be stalled until the resource becomes available again.
The XGATE offers a high access rate to the MCU’s internal RAM. Depending on the bus load, the RISC
core can perform up to two RAM accesses per S12X_CPU bus cycle.
Bus accesses to peripheral registers or flash are slower. A transfer rate of one bus access per S12X_CPU
cycle can not be exceeded.
The XGATE module is intended to execute short interrupt service routines that are triggered by peripheral
modules or by software.
10.4.2
1. With the exception of PRR registers (see Section “S12X_MMC”).
376
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
XGATE RISC Core
Programmer’s Model
1
. Whenever the S12X_CPU and the RISC core access the same resource, the RISC core
15
15
15
15
15
15
15
15
Register Block
MC9S12XE-Family Reference Manual , Rev. 1.23
R7
R0 = 0
R6
R5
R4
R3
R2
R1
Figure 10-22. Programmer’s Model
(Stack Pointer)
(Data Pointer)
0
0
0
0
0
0
0
0
Section 10.8, “Instruction
15
1
Program Counter
PC
Condition
Register
N Z
3 2
Code
Set”).
V C
1 0
0
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