MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 381

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MC9S12XEQ512CAL

Manufacturer Part Number
MC9S12XEQ512CAL
Description
MCU 16BIT 512K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEQ512CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
91
Eeprom Memory Size
4KB
Ram Memory Size
32KB
Cpu Speed
50MHz
No. Of Timers
3
No. Of Pwm Channels
8
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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10.5
10.5.1
XGATE threads are triggered by interrupt requests which are routed to the XGATE module (see
S12X_INT Section). Only a subset of the MCU’s interrupt requests can be routed to the XGATE. Which
specific interrupt requests these are and which channel ID they are assigned to is documented in Section
“Interrupts” of the device overview.
10.5.2
There are three types of interrupt requests which can be triggered by the XGATE module:
All outgoing XGATE interrupts, except software error interrupts, can be disabled by the XGIE bit in the
XGATE module control register (XGMCTL, see
(XGMCTL)”).
10.6
The XGATE debug mode is a feature to allow debugging of application code.
10.6.1
In debug mode the RISC core will be halted and the following debug features will be enabled:
1. Only possible if MCU is unsecured
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
4. Channel interrupts
5. Software triggers
6. Software error interrupt
For each XGATE channel there is an associated interrupt flag in the XGATE interrupt flag vector
(XGIF, see
set through the "SIF" instruction by the RISC core. They are typically used to flag an interrupt to
the S12X_CPU when the XGATE has completed one of its task.
Software triggers are interrupt flags, which can be set and cleared by software (see
Section 10.3.1.9, “XGATE Software Trigger Register
trigger XGATE tasks by the S12X_CPU software. However these interrupts can also be routed to
the S12X_CPU (see S12X_INT Section) and triggered by the XGATE software.
The software error interrupt signals to the S12X_CPU the detection of an error condition in the
XGATE application code (see
interrupt. Executing the interrupt service routine will automatically reset the interrupt line.
Read and Write accesses to RISC core registers (XGCCR, XGPC, XGR1–XGR7)
All RISC core registers can be modified. Leaving debug mode will cause the RISC core to continue
program execution with the modified register values.
Interrupts
Debug Mode
Incoming Interrupt Requests
Outgoing Interrupt Requests
Debug Features
Section 10.3.1.8, “XGATE Channel Interrupt Flag Vector
MC9S12XE-Family Reference Manual Rev. 1.23
Section 10.4.5, “Software Error
Section 10.3.1.1, “XGATE Control Register
(XGSWT)”). They are typically used to
Detection”). This is a non-maskable
(XGIF)”). These flags can be
Chapter 10 XGATE (S12XGATEV3)
1
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