MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 391

• Manufacturer Part Number: MC9S12XEQ512CAL
• Description: MCU 16BIT 512K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEQ512CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 32KB
• Cpu Speed: 50MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADC
Operation
RS1 + RS2 + C ⇒ RD
Adds the content of register RS1, the content of register RS2 and the value of the Carry bit using binary
addition and stores the result in the destination register RD. The Zero Flag is also carried forward from the
previous operation allowing 32 and more bit additions.
Example:
CCR Effects
Code and CPU Cycles
Freescale Semiconductor
N:
Z:
V:
C:
ADC RD, RS1, RS2
N
∆
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000 and Z was set before this operation; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS1[15] & RS2[15] & RD[15]
Set if there is a carry from bit 15 of the result; cleared otherwise.
RS1[15] & RS2[15] | RS1[15] & RD[15]
Z
∆
ADD
ADC
BCC
V
∆
Source Form
C
∆
R6,R2,R2
R7,R3,R3 ; R7:R6 = R5:R4 + R3:R2
new
; conditional branch on 32 bit addition
MC9S12XE-Family Reference Manual Rev. 1.23
| RS1[15] & RS2[15] & RD[15]
Address
Mode
new
TRI
| RS2[15] & RD[15]
Add with Carry
0
0
0
1
new
new
1
Machine Code
RD
RS1
Chapter 10 XGATE (S12XGATEV3)
RS2
ADC
1
1
Cycles
P
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