MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 474

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MC9S12XEQ512CAL

Manufacturer Part Number
MC9S12XEQ512CAL
Description
MCU 16BIT 512K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEQ512CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
91
Eeprom Memory Size
4KB
Ram Memory Size
32KB
Cpu Speed
50MHz
No. Of Timers
3
No. Of Pwm Channels
8
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
11.3
This section provides a detailed description of all registers accessible in the S12XECRG.
11.3.1
Figure 11-2
474
2. FORBYP and CTCTL are intended for factory test purposes only.
Address
0x000A
0x000B
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
FORBYP
Memory Map and Registers
POSTDIV
ARMCOP
CRGFLG
COPCTL
CRGINT
CLKSEL
PLLCTL
CTCTL
RTICTL
REFDV
SYNR
Name
Module Memory Map
gives an overview on all S12XECRG registers.
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
2
2
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R
PLLSEL
RTDEC
WCOP
RTIE
CME
Bit 7
RTIF
Bit 7
VCOFRQ[1:0]
REFFRQ[1:0]
0
0
0
0
MC9S12XE-Family Reference Manual , Rev. 1.23
= Unimplemented or Reserved
RSBCK
Figure 11-2. CRG Register Summary
PLLON
PORF
PSTP
RTR6
Bit 6
6
0
0
0
0
0
WRTMASK
XCLKS
RTR5
LVRF
FM1
Bit 5
5
0
0
0
0
0
0
NOTE
LOCKIE
LOCKIF
RTR4
FM0
Bit 4
4
0
0
0
0
0
FSTWKP
PLLWAI
LOCK
RTR3
Bit 3
3
0
0
0
0
0
SYNDIV[5:0]
REFDIV[5:0]
POSTDIV[4:0]
RTR2
ILAF
PRE
CR2
Bit 2
2
0
0
0
0
0
Freescale Semiconductor
RTIWAI
SCMIF
SCMIE
RTR1
PCE
CR1
Bit 1
1
0
0
0
COPWAI
SCME
RTR0
SCM
Bit 0
CR0
Bit 0
0
0
0
0

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