MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 500

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MC9S12XEQ512CAL

Manufacturer Part Number
MC9S12XEQ512CAL
Description
MCU 16BIT 512K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEQ512CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
91
Eeprom Memory Size
4KB
Ram Memory Size
32KB
Cpu Speed
50MHz
No. Of Timers
3
No. Of Pwm Channels
8
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
11.6.1
11.6.1.1
The S12XECRG generates a real time interrupt when the selected interrupt time period elapses. RTI
interrupts are locally disabled by setting the RTIE bit to zero. The real time interrupt flag (RTIF) is set to1
when a timeout occurs, and is cleared to 0 by writing a 1 to the RTIF bit.
The RTI continues to run during Pseudo Stop Mode if the PRE bit is set to 1. This feature can be used for
periodic wakeup from Pseudo Stop if the RTI interrupt is enabled.
11.6.1.2
The S12XECRG generates a IPLL Lock interrupt when the LOCK condition of the IPLL has changed,
either from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting
the LOCKIE bit to zero. The IPLL Lock interrupt flag (LOCKIF) is set to1 when the LOCK condition has
changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.
11.6.1.3
The S12XECRG generates a Self Clock Mode interrupt when the SCM condition of the system has
changed, either entered or exited Self Clock Mode. SCM conditions are caused by a failing clock quality
check after power on reset (POR) or low voltage reset (LVR) or recovery from Full Stop Mode (PSTP =
0) or Clock Monitor failure. For details on the clock quality check refer to
Checker”. If the clock monitor is enabled (CME = 1) a loss of external clock will also cause a SCM
condition (SCME = 1).
SCM interrupts are locally disabled by setting the SCMIE bit to zero. The SCM interrupt flag (SCMIF) is
set to1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit.
500
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Description of Interrupt Operation
Real Time Interrupt
IPLL Lock Interrupt
Self Clock Mode Interrupt
MC9S12XE-Family Reference Manual , Rev. 1.23
Section 11.4.1.4, “Clock Quality
Freescale Semiconductor

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