MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 604

• Manufacturer Part Number: MC9S12XEQ512CAL
• Description: MCU 16BIT 512K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEQ512CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 32KB
• Cpu Speed: 50MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
attempt to engage the bus is failed. When considering these cases, the slave service routine should test the
IBAL first and the software should clear the IBAL bit if it is set.
604
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Dummy Read
From IBDR
Switch To
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Rx Mode
Y
Byte To IBDR
(Master Rx)
Transmitted
Addr Cycle
Last Byte
Write Next
RXAK=0
End Of
?
?
?
Y
N
N
Stop Signal
TX
Generate
Y
N
Figure 15-15. Flow-Chart of Typical IIC Interrupt Routine
Tx/Rx
Set TXAK =1
?
Y
MC9S12XE-Family Reference Manual , Rev. 1.23
Byte To Be Read
Byte To Be Read
From IBDR
Read Data
And Store
2nd Last
RX
Last
?
?
N
N
Stop Signal
Generate
Y
Y
RTI
Master
Mode
Clear
IBIF
?
Write Data
(Read)
To IBDR
Set TX
Mode
N
Y
N
7-bit address transfer
Clear IBAL
IAAS=1
Dummy Read
SRW=1
From IBDR
?
Set RX
?
Mode
N
N
(Write)
Y
10-bit
address?
Tx Next
Byte
Y
Y
Y
Dummy Read
From IBDR
Arbitration
ACK From
Switch To
Receiver
IAAS=1
Rx Mode
TX/RX
Lost
?
?
?
?
N
N
N
TX
Data Transfer
Freescale Semiconductor
From IBDR
Read Data
And Store
Dummy Read
From IBDR
RX
N
set RX
Mode
10-bit address transfer
IBDR==
11110xx1?
set TX
Mode
Write Data
To IBDR
Y
Y