MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 777

• Manufacturer Part Number: MC9S12XEQ512CAL
• Description: MCU 16BIT 512K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEQ512CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 32KB
• Cpu Speed: 50MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.4.2
The SPI operates in slave mode when the MSTR bit in SPI control register 1 is clear.
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drive the MOSI and SCK lines. In this case, the SPI immediately switches to slave mode, by
clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional
mode). So the result is that all outputs are disabled and SCK, MOSI, and MISO are inputs. If a
transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is
forced into idle state.
This mode fault error also sets the mode fault (MODF) flag in the SPI status register (SPISR). If
the SPI interrupt enable bit (SPIE) is set when the MODF flag becomes set, then an SPI interrupt
sequence is also requested.
When a write to the SPI data register in the master occurs, there is a half SCK-cycle delay. After
the delay, SCK is started within the master. The rest of the transfer operation differs slightly,
depending on the clock format specified by the SPI clock phase bit, CPHA, in SPI control register 1
(see
Serial clock
In slave mode, SCK is the SPI clock input from the master.
MISO, MOSI pin
In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI)
is determined by the SPC0 bit and BIDIROE bit in SPI control register 2.
SS pin
The SS pin is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI
must be low. SS must remain low until the transmission is complete. If SS goes high, the SPI is
forced into idle state.
The SS input also controls the serial data output pin, if SS is high (not selected), the serial data
output pin is high impedance, and, if SS is low, the first bit in the SPI data register is driven out of
the serial data output pin. Also, if the slave is not selected (SS is high), then the SCK input is
ignored and no internal shifting of the SPI shift register occurs.
Although the SPI is capable of duplex operation, some SPI peripherals are capable of only
receiving SPI data in a slave mode. For these simpler devices, there is no serial data out pin.
Slave Mode
Section 21.4.3, “Transmission
A change of the bits CPOL, CPHA, SSOE, LSBFE, XFRW, MODFEN,
SPC0, or BIDIROE with SPC0 set, SPPR2-SPPR0 and SPR2-SPR0 in
master mode will abort a transmission in progress and force the SPI into idle
state. The remote slave cannot detect this, therefore the master must ensure
that the remote slave is returned to idle state.
When peripherals with duplex capability are used, take care not to
simultaneously enable two receivers whose serial outputs drive the same
system slave’s serial data output line.
MC9S12XE-Family Reference Manual Rev. 1.23
Formats”).
NOTE
NOTE
Chapter 21 Serial Peripheral Interface (S12SPIV5)
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