MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 833

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MC9S12XEQ512CAL

Manufacturer Part Number
MC9S12XEQ512CAL
Description
MCU 16BIT 512K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEQ512CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
91
Eeprom Memory Size
4KB
Ram Memory Size
32KB
Cpu Speed
50MHz
No. Of Timers
3
No. Of Pwm Channels
8
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 24
128 KByte Flash Module (S12XFTM128K2V1)
Freescale Semiconductor
Revision
Number
V01.10
V01.11
V01.12
30 Nov 2007
19 Dec 2007
25 Sep 2009
Revision
Date
24.1.2.2/24-835
24.3.2.1/24-845
24.4.2.4/24-872
24.4.2.6/24-873
24.3.2.1/24-845
24.4.1.2/24-864
24.1.3/24-836
24.4.2/24-869
24.4.2/24-869
24.4.2/24-869
24.4.2/24-869
24.3.1/24-838
24.1.3/24-836
24.3.1/24-838
24.3.1/24-838
24.3.2/24-843
24.4.2.11/24-
24.4.2.11/24-
24.4.2.11/24-
24.4.2.19/24-
24.1/24-834
24.6/24-892
Sections
Affected
MC9S12XE-Family Reference Manual , Rev. 1.23
877
877
877
886
Table 24-1. Revision History
- Correction
- Removed Load Data Field command 0x05
- Updated Command Error Handling tables based on parent-child relationship
with FTM256K2
- Corrected Error Handling table for Full Partition D-Flash, Partition D-Flash,
and EEPROM Emulation Query commands
- Corrected maximum allowed ERPART for Full Partition D-Flash and Partition
D-Flash commands
- Corrected P-Flash IFR Accessibility table
- Corrected Buffer RAM size in Feature List
- Corrected EEE Resource Memory Map
- Changed D-Flash size from 16Kbytes to 32Kbytes
- Corrected P-Flash Memory Map
- Change references for D-Flash from 16 Kbytes to 32 Kbytes
- Clarify single bit fault correction for P-Flash phrase
- Expand FDIV vs OSCCLK Frequency table
- Add statement concerning code runaway when executing Read Once
command from Flash block containing associated fields
- Add statement concerning code runaway when executing Program Once
command from Flash block containing associated fields
- Add statement concerning code runaway when executing Verify Backdoor
Access Key command from Flash block containing associated fields
- Relate Key 0 to associated Backdoor Comparison Key address
- Change “power down reset” to “reset”
- Add ACCERR condition for Disable EEPROM Emulation command
The following changes were made to clarify module behavior related to Flash
register access during reset sequence and while Flash commands are active:
- Add caution concerning register writes while command is active
- Writes to FCLKDIV are allowed during reset sequence while CCIF is clear
- Add caution concerning register writes while command is active
- Writes to FCCOBIX, FCCOBHI, FCCOBLO registers are ignored during
reset sequence
toTable 24-6
Description of Changes
833

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