MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 84

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MC9S12XEQ512CAL

Manufacturer Part Number
MC9S12XEQ512CAL
Description
MCU 16BIT 512K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEQ512CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
91
Eeprom Memory Size
4KB
Ram Memory Size
32KB
Cpu Speed
50MHz
No. Of Timers
3
No. Of Pwm Channels
8
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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1. 16 bits vector address based
2. For detailed description of XGATE channel ID refer to XGATE Block Guide
Chapter 1 Device Overview MC9S12XE-Family
Vector Address
1.6.3
When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block
descriptions for register reset states.
On each reset, the Flash module executes a reset sequence to load Flash configuration registers and
initialize the buffer RAM EEE partition, if required.
1.6.3.1
On each reset, the Flash module will hold CPU activity while loading Flash module registers and
configuration from the Flash memory. The duration of this phase is given as t
parameter specification. If double faults are detected in the reset phase, Flash module protection and
security may be active on leaving reset. This is explained in more detail in the Flash module section.
1.6.3.2
During this phase of the reset sequence (following on from the core hold phase) the CPU can execute
instructions while the FTM initialization completes and, if configured for EEE operation, the EEE RAM
84
Vector base + $4C
Vector base + $3E
Vector base + $3C
Vector base + $3A
Vector base + $42
Vector base + $16
Vector base + $14
Vector base + $12
Vector base + $10
Vector base+ $4E
Vector base+ $4A
Vector base+ $48
Vector base+ $46
Vector base+ $44
Vector base+ $40
Vector base+ $18
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
to
Effects of Reset
Flash Configuration Reset Sequence (Core Hold Phase)
EEE Reset Sequence Phase (Core Active Phase)
(1)
Channel
XGATE
ID
$1F
$1E
$27
$26
$25
$24
$23
$22
$21
$20
(2)
Table 1-14. Interrupt Vector Locations (Sheet 4 of 4)
TIM Pulse accumulator A overflow
TIM Pulse accumulator input edge
MC9S12XE-Family Reference Manual , Rev. 1.23
XGATE software error interrupt
System Call Interrupt (SYS)
ATD0 Compare Interrupt
ATD1 Compare Interrupt
TIM timer channel 3
TIM timer channel 4
TIM timer channel 5
TIM timer channel 6
TIM timer channel 7
MPU Access Error
TIM timer overflow
Spurious interrupt
Interrupt Source
Reserved
Mask
None
None
CCR
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
ATD0CTL2 (ACMPIE)
ATD1CTL2 (ACMPIE)
PACTL (PAOVI)
Local Enable
TSRC2 (TOF)
PACTL (PAI)
TIE (C3I)
TIE (C4I)
TIE (C5I)
TIE (C6I)
TIE (C7I)
None
None
None
None
RST
in the device electrical
Freescale Semiconductor
Wake up
STOP
Yes
Yes
No
No
No
No
No
No
No
No
No
No
Wake up
WAIT
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No

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