MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 849

• Manufacturer Part Number: MC9S12XEQ512CAL
• Description: MCU 16BIT 512K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEQ512CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 32KB
• Cpu Speed: 50MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.3.2.5
The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array
read access from the CPU or XGATE.
CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not
writable.
Freescale Semiconductor
ECCRIX[2:0]
Offset Module Base + 0x0004
Reset
IGNSF
Field
Field
CCIE
2-0
7
4
W
R
CCIE
ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is
being read. See
Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command
has completed.
0 Command complete interrupt disabled
1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see
Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see
Section
0 All single bit faults detected during array reads are reported
1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be
Flash Configuration Register (FCNFG)
0
7
generated
24.3.2.8).
= Unimplemented or Reserved
0
0
6
Section 24.3.2.13, “Flash ECC Error Results Register
Figure 24-9. Flash Configuration Register (FCNFG)
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 24-14. FECCRIX Field Descriptions
Table 24-15. FCNFG Field Descriptions
0
0
5
IGNSF
0
4
Description
Description
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1)
0
0
3
(FECCR),” for more details.
0
0
2
FDFD
0
1
Section
24.3.2.7)
FSFD
0
0
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