MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 857

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MC9S12XEQ512CAL

Manufacturer Part Number
MC9S12XEQ512CAL
Description
MCU 16BIT 512K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEQ512CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
91
Eeprom Memory Size
4KB
Ram Memory Size
32KB
Cpu Speed
50MHz
No. Of Timers
3
No. Of Pwm Channels
8
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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24.3.2.9.1
The general guideline is that P-Flash protection can only be added and not removed.
all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the
FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario.
See the FPHS and FPLS bit descriptions for additional restrictions.
24.3.2.10 EEE Protection Register (EPROT)
The EPROT register defines which buffer RAM EEE partition areas are protected against writes.
All bits in the EPROT register are readable and writable except for RNV[6:4] which are only readable. The
EPOPEN and EPDIS bits can only be written to the protected state. The EPS bits can be written anytime
until the EPDIS bit is cleared. If the EPOPEN bit is cleared, the state of the EPDIS and EPS bits is
irrelevant.
During the reset sequence, the EPROT register is loaded from the EEE protection byte in the Flash
configuration field at global address 0x7F_FF0D located in P-Flash memory (see
by reset condition F in
sequence, the P-Flash sector containing the EEE protection byte must be unprotected, then the EEE
protection byte must be programmed. If a double bit fault is detected while reading the P-Flash phrase
Freescale Semiconductor
Offset Module Base + 0x0009
Reset
W
R
EPOPEN
F
7
P-Flash Protection Restrictions
1. Allowed transitions marked with X, see
Protection
Scenario
From
= Unimplemented or Reserved
0
1
2
3
4
5
6
7
Figure
F
6
Table 24-23. P-Flash Protection Scenario Transitions
Figure 24-15. EEE Protection Register (EPROT)
24-15. To change the EEE protection that will be loaded during the reset
MC9S12XE-Family Reference Manual , Rev. 1.23
X
X
0
RNV[6:4]
F
5
X
X
X
X
1
X
X
X
X
2
To Protection Scenario
F
4
Figure 24-14
X
X
X
X
X
X
X
X
3
EPDIS
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1)
X
X
X
X
4
for a definition of the scenarios.
F
3
(1)
5
X
X
F
2
X
X
6
Table
Table 24-23
EPS[2:0]
X
7
F
1
24-3) as indicated
specifies
F
0
857

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