MC908LJ24CFUE Freescale Semiconductor, MC908LJ24CFUE Datasheet - Page 294

• Manufacturer Part Number: MC908LJ24CFUE
• Description: IC MCU 24K FLASH 8MHZ SPI 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ24CFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Controller Family/series: HC08
• No. Of I/o's: 40
• Ram Memory Size: 768Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Serial Peripheral Interface Module (SPI)
14.6.2 Transmission Format When CPHA = 0
Data Sheet
294
NOTE:
The clock phase (CPHA) control bit selects one of two fundamentally
different transmission formats. The clock phase and polarity should be
identical for the master SPI device and the communicating slave device.
In some cases, the phase and polarity are changed between
transmissions to allow a master device to communicate with peripheral
slaves having different requirements.
Before writing to the CPOL bit or the CPHA bit, disable the SPI by
clearing the SPI enable bit (SPE).
Figure 14-4
figure should not be used as a replacement for data sheet parametric
information.
Two waveforms are shown for SPSCK: one for CPOL = 0 and another
for CPOL = 1. The diagram may be interpreted as a master or slave
timing diagram since the serial clock (SPSCK), master in/slave out
(MISO), and master out/slave in (MOSI) pins are directly connected
between the master and the slave. The MISO signal is the output from
the slave, and the MOSI signal is the output from the master. The SS line
is the slave select input to the slave. The slave SPI drives its MISO
output only when its slave select input (SS) is at logic 0, so that only the
selected slave drives to the master. The SS pin of the master is not
shown but is assumed to be inactive. The SS pin of the master must be
high or must be reconfigured as general-purpose I/O not affecting the
SPI. (See
edge is the MSB capture strobe. Therefore, the slave must begin driving
its data before the first SPSCK edge, and a falling edge on the SS pin is
used to start the slave data transmission. The slave’s SS pin must be
toggled back to high and then low again between each byte transmitted
as shown in
Serial Peripheral Interface Module (SPI)
14.8.2 Mode Fault
Figure
shows an SPI transmission in which CPHA is logic 0. The
14-5.
Error.) When CPHA = 0, the first SPSCK
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor