MC908LJ24CFUE Freescale Semiconductor, MC908LJ24CFUE Datasheet - Page 330

IC MCU 24K FLASH 8MHZ SPI 64-QFP

MC908LJ24CFUE

Manufacturer Part Number
MC908LJ24CFUE
Description
IC MCU 24K FLASH 8MHZ SPI 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908LJ24CFUE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
40
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Processor Series
HC08LJ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Operating Supply Voltage
3.3 V, 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
Controller Family/series
HC08
No. Of I/o's
40
Ram Memory Size
768Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Multi-Master IIC Interface (MMIIC)
15.6 Programming Considerations
Data Sheet
330
In slave mode, the data in MMDRR is:
In master mode, the data in the MMDRR is:
When the MMDRR is read by the CPU, the receive buffer full flag is
cleared (MMRXBF = 0), and the next received data is loaded to the
MMDRR. Each time when new data is loaded to the MMDRR, the
MMRXIF interrupt flag is set, indicating that new data is available in
MMDRR.
The sequence of events for slave receive and master receive are
illustrated in
When the MMIIC module detects an arbitration loss in master mode, it
will release both SDA and SCL lines immediately. But if there are no
further STOP conditions detected, the module will hang up. Therefore, it
is recommended to have time-out software to recover from such ill
condition. The software can start the time-out counter by looking at the
MMBB (Bus Busy) flag in the MIMCR and reset the counter on the
completion of one byte transmission. If a time-out occur, software can
clear the MMEN bit (disable MMIIC module) to release the bus, and
hence clearing the MMBB flag. This is the only way to clear the MMBB
flag by software if the module hangs up due to a no STOP condition
received. The MMIIC can resume operation again by setting the MMEN
bit.
the calling address from the master when the address match flag
is set (MMATCH = 1); or
the last data received when MMATCH = 0.
the last data received.
Multi-Master IIC Interface (MMIIC)
Figure
15-8.
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor

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