MC908LJ24CFUE Freescale Semiconductor, MC908LJ24CFUE Datasheet - Page 67

IC MCU 24K FLASH 8MHZ SPI 64-QFP

MC908LJ24CFUE

Manufacturer Part Number
MC908LJ24CFUE
Description
IC MCU 24K FLASH 8MHZ SPI 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908LJ24CFUE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
40
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Processor Series
HC08LJ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Operating Supply Voltage
3.3 V, 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
Controller Family/series
HC08
No. Of I/o's
40
Ram Memory Size
768Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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3.1 Contents
3.2 Introduction
3.3 Functional Description
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
Data Sheet — MC68HC908LJ24
NOTE:
NOTE:
Section 3. Random-Access Memory (RAM)
3.2
3.3
This section describes the 768 bytes of RAM (random-access memory).
Addresses $0080 through $037F are RAM locations. The location of the
stack RAM is programmable. The 16-bit stack pointer allows the stack to
be anywhere in the 64K-byte memory space.
For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 128 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF out of page zero, direct addressing mode
instructions can efficiently access all page zero RAM locations. Page
zero RAM, therefore, provides ideal locations for frequently accessed
global variables.
Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.
For M6805 compatibility, the H register is not stacked.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Random-Access Memory (RAM)
Data Sheet
67

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