MC68HC711D3CFNE3 Freescale Semiconductor, MC68HC711D3CFNE3 Datasheet
MC68HC711D3CFNE3
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MC68HC711D3 MC68HC11D3 MC68HC11D0 MC68L11D0 Data Sheet HC11 Microcontrollers MC68HC711D3 Rev. 2.1 07/2005 freescale.com ...
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...
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... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2005. All rights reserved. Freescale Semiconductor MC68HC711D3 Data Sheet, Rev ...
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... Added the following appendices: Appendix A. MC68HC11D3 and MC68HC11D0 Appendix B. MC68L11D0 July, 2.1 Updated to meet Freescale identity guidelines. 2005 4 Description MC68HC711D3 Data Sheet, Rev. 2.1 Page Number(s) N/A Throughout 133 137 143 Throughout Freescale Semiconductor ...
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... Chapter 5 Input/Output (I/O) Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Chapter 6 Serial Communications Interface (SCI .65 Chapter 7 Serial Peripheral Interface (SPI Chapter 8 Programmable Timer Chapter 9 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Chapter 10 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 121 Appendix A MC68HC11D3 and MC68HC11D0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Appendix B MC68L11D0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Freescale Semiconductor MC68HC711D3 Data Sheet, Rev. 2.1 5 ...
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... List of Chapters 6 MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
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... Configuration Control Register 2.4 Programmable Read-Only Memory (PROM 2.4.1 Programming an Individual EPROM Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.4.2 Programming the EPROM with Downloaded Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.4.3 PROM Programming Control Register Freescale Semiconductor Chapter 1 General Description , and STBY Chapter 2 Operating Modes and Memory MC68HC711D3 Data Sheet, Rev. 2.1 ) ...
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... Software Interrupt (SWI 4.3.2 Illegal Opcode Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.3.3 Real-Time Interrupt (RTI 4.3.4 Interrupt Mask Bits in the CCR 4.3.5 Priority Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.3.6 Highest Priority I Interrupt and Miscellaneous Register (HPRIO Chapter 3 Central Processor Unit (CPU) Chapter 4 MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
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... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.3 SPI Transfer Formats 7.4 Clock Phase and Polarity Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.5 SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.5.1 Master In/Slave Out (MISO 7.5.2 Master Out/Slave In (MOSI Freescale Semiconductor Chapter 5 Input/Output (I/O) Ports Chapter 6 Chapter 7 Serial Peripheral Interface (SPI) MC68HC711D3 Data Sheet, Rev. 2.1 9 ...
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... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.2 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.3 Functional Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 9.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 9.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.6 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.7 Peripheral Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10 Chapter 8 Programmable Timer Chapter 9 Electrical Characteristics MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
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... DC Electrical Characteristics 131 B.2.3 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 B.2.4 Peripheral Port Timing 133 B.2.5 Expansion Bus Timing 134 B.2.6 Serial Peripheral Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 B.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Freescale Semiconductor Chapter 10 Appendix A MC68HC11D3 and MC68HC11D0 Appendix B MC68L11D0 MC68HC711D3 Data Sheet, Rev. 2.1 11 ...
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... Table of Contents 12 MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
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... Structure Refer to Figure 1-1, which shows the structure of the MC68HC711D3 MCU. Freescale Semiconductor and Appendix B MC68L11D0. MC68HC711D3 Data Sheet, Rev. 2.1 Appendix A 13 ...
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... PERIODIC INTERRUPT MC68HC711D3 CPU CORE DATA DIRECTION REGISTER C PORT C Figure 1-4 for pin assignments. MC68HC711D3 Data Sheet, Rev. 2 KBYTES EPROM OR OTPROM 192 BYTES STATIC RAM SERIAL PERIPHERAL COMMUNICATIONS INTERFACE INTERFACE (SPI) TxD DATA DIRECTION REGISTER D PORT D Freescale Semiconductor SERIAL (SCI) RxD ...
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... Figure 1-2. Pin Assignments for 40-Pin Plastic DIP XIRQ/V PD7/R/W PD6/AS RESET Figure 1-3. Pin Assignments for 44-Pin PLCC Freescale Semiconductor XTAL SS PC0 2 39 EXTAL 38 E PC1 3 37 MODA/LIR PC2 4 PC3 5 36 MODB/V PC4 6 35 PB0 34 PB1 PC5 7 33 PB2 PC6 ...
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... Highest Priority I Interrupt and Miscellaneous Register (HPRIO) 16 PC4 1 PC5 2 PC6 3 4 PC7 5 6 PD7 7 PD6 8 9 IRQ PD0 10 PD1 , V , and and the power supply (+5 V ±10%) and MC68HC711D3 Data Sheet, Rev. 2.1 PB0 PB1 32 PB2 31 PB3 30 PB4 29 PB5 28 PB6 27 PB7 PA0 24 PA1 23 for details. Freescale Semiconductor is SS ...
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... IRQE bit of the OPTION register. IRQ is always configured to level-sensitive triggering at reset. While the programmable read-only memory (PROM) is being programmed, this pin provides the chip enable (CE) signal. To prevent accidental programming of the PROM during reset, an external resistor is required on IRQ to pull the pin to V Freescale Semiconductor CMOS-COMPATIBLE EXTERNAL OSCILLATOR ...
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... Ports B, C, and two bits of port D are available for I/O functions only in single-chip and bootstrap modes. 18 input is used to retain random-access memory STBY for further information. for further information. NOTE MC68HC711D3 Data Sheet, Rev. 2 the MCU. To avoid PP during normal operation unless DD ) STBY Chapter 5 Freescale Semiconductor ...
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... In the 40-pin package, pins PA4 and PA6 are not bonded. Their associated I/O and output compare functions are not available externally. They can still be used as internal software timers, however. Freescale Semiconductor Input/Output Lines (PA7–PA0, PB7–PB0, PC7–PC0, and PD7–PD0) Table 1-1. Port Signal Functions ...
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... General Description 20 MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
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... B pins. Low-order address bits and the bidirectional data bus are multiplexed on port C. The AS pin provides the control output used in demultiplexing the low-order address. The R/W pin is used to control the direction of data transfer on the port C bus. Freescale Semiconductor Table 2-1. Mode Selection MODB ...
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... Pulse accumulator overflow Timer overflow Timer output compare 5/input capture 4 Timer output compare 4 Timer output compare 3 Timer output compare 2 Timer output compare 1 Timer input capture 3 Timer input capture 2 Timer input capture 1 MC68HC711D3 Data Sheet, Rev. 2.1 Table 2-2), so that the user PP Freescale Semiconductor ...
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... This block may be mapped to any 4-K boundary in memory, but reset locates it at $0000–$003F. This mappability factor and the default starting addresses are indicated by the use of a bold 0 as the starting character of a register’s address. Freescale Semiconductor Vector Real-time interrupt ...
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... KBYTES PROM (ROM) $7000 PRESENT AT RESET AND MAY BE DISABLED BY EPON (ROM ON) BIT IN CONFIG REGISTER. $7FFF INTERRUPT VECTORS ARE EXTERNAL. 256-BYTES $BFC0 $BF00 SPECIAL MODES BOOT ROM INTERRUPT $BFFF VECTORS $BFFF $BFC0 $BF00 4-KBYTES NORMAL MODES PROM (ROM) INTERRUPT $BFFF VECTORS $BFFF Freescale Semiconductor ...
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... Timer Compare Force Register $000B (CFORC) See page 93. Output Compare 1 Mask Register $000C (OC1M) See page 93. Output Compare 1 Data Register $000D (OC1D) See page 94. Figure 2-2. Register and Control Bit Assignments (Sheet Freescale Semiconductor Bit Read: PA7 PA6 PA5 Write: Reset: Hi ...
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... Bit 1 Unaffected by reset Bit 12 Bit 11 Bit 10 Bit Bit 4 Bit 3 Bit 2 Bit Bit 12 Bit 11 Bit 10 Bit Bit 4 Bit 3 Bit 2 Bit Reserved U = Unaffected Freescale Semiconductor Bit 0 Bit 8 0 Bit 0 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 15 1 Bit 0 1 Bit 8 1 Bit 0 1 ...
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... Timer Interrupt Flag 1 Register $0023 (TFLG1) See page 96. Timer Interrupt Mask 2 Register $0024 (TMSK2) See page 96. Timer Interrupt Flag 2 Register $0025 (TFLG2) See page 97. Figure 2-2. Register and Control Bit Assignments (Sheet Freescale Semiconductor Bit Read: Bit 15 Bit 14 Bit 13 Write: Reset ...
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... CPOL CPHA SPR1 MODF Bit 4 Bit 3 Bit 2 Bit 1 Unaffected by reset SCP0 RCKB SCR2 SCR1 WAKE ILIE TE RE RWU IDLE R4/T4 R3/T3 R2/T2 R1/T1 Unaffected by reset DLY CME 0 CR1 Reserved U = Unaffected R Freescale Semiconductor Bit 0 RTR0 0 Bit 0 SPR0 Bit 0 SCR0 SBK R0/T0 R CR0 0 ...
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... MCU memory map. It can be written to only once within the first 64 E-clock cycles after a reset in normal modes. Thereafter, it becomes a read-only register. Address: $003D Bit 7 Read: RAM3 Write: Reset: 0 Figure 2-3. RAM and I/O Mapping Register (INIT) Freescale Semiconductor Bit Read: Bit 7 Bit 6 Bit 5 Write: Reset: 0 ...
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... It is writable only once after reset in these modes (SMOD = 0). In the special modes (test and bootstrap) (SMOD = 1), this bit comes out of reset set, and is writable any time COP system is disabled COP system is enabled, reset forced on timeout. 30 NOTE MC68HC711D3 Data Sheet, Rev. 2 Bit 0 NOCOP ROMON Freescale Semiconductor ...
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... LDAB #$21 STAB $003B JSR DLYEP CLR $003B Freescale Semiconductor NOTE Set ELAT bit (PGM = 0) to enable EPROM latches. Store data to EPROM address Set PGM bit with ELAT = 1 to enable EPROM programming voltage Delay 2–4 ms Turn off programming voltage and set to READ mode MC68HC711D3 Data Sheet, Rev ...
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... EXROW — Select Extra Row Bit This bit is reserved for testing. PGM — EPROM (OTPROM) Program Command Bit This bit may be written only when ELAT = Programming power is switched on to PROM array Programming power is switched off ELAT EXCOL EXROW MC68HC711D3 Data Sheet, Rev. 2 Bit PGM Freescale Semiconductor ...
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... M68HC11 CPU registers are an integral part of the CPU and are not addressed as if they were memory locations. The seven registers, discussed in the following paragraphs, are shown in 7 ACCUMULATOR CONDITION CODE REGISTER Freescale Semiconductor 0 7 ACCUMULATOR B DOUBLE ACCUMULATOR D INDEX REGISTER X INDEX REGISTER Y STACK POINTER PROGRAM COUNTER 7 ...
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... CPU registers are pushed onto the stack, and execution continues at the address specified by the vector for the interrupt. 34 3.4 Opcodes and Operands MC68HC711D3 Data Sheet, Rev. 2.1 for further Figure 3 Freescale Semiconductor ...
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... RTS, RETURN FROM SUBROUTINE SUBROUTINE PC $39 = RTS SWI, SOFTWARE INTERRUPT MAIN PROGRAM PC $3F = SWI RTN WAI, WAIT FOR INTERRUPT MAIN PROGRAM PC $3E = WAI RTN Freescale Semiconductor RTI, RETURN FROM INTERRUPT INTERRUPT PROGRAM PC STACK SP-2 RTN SP-1 L RTN SP H JMP, JUMP INDXD,X ...
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... For these operations, only = and ≠ conditions can be determined. 36 Table 3-1. Reset Vector Comparison POR or RESET Pin Clock Monitor $FFFE, $FFFF $FFFC, $FFFD $BFFE, $BFFF $BFFC, $FFFD Table 3-2, which shows what condition codes are MC68HC711D3 Data Sheet, Rev. 2.1 COP Watchdog $FFFA, $FFFB $BFFA, $FFFB Freescale Semiconductor ...
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... STOP is disabled by default. 3.3 Data Types The M68HC11 CPU supports four data types: 1. Bit data 2. 8-bit and 16-bit signed and unsigned integers 3. 16-bit unsigned fractions 4. 16-bit addresses Freescale Semiconductor MC68HC711D3 Data Sheet, Rev. 2.1 Data Types Chapter 4 Resets, Interrupts, and 37 ...
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... In most applications, this 256-byte area is reserved for frequently referenced data. In M68HC11 MCUs, the memory map can be configured for combinations of internal registers, RAM, or external memory to occupy these addresses. 38 MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
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... ⇒ IX ABX Add ( ⇒ IY ABY Add ⇒ A ADCA (opr) Add with Carry ⇒ B ADCB (opr) Add with Carry ⇒ A ADDA (opr) Add Memory to A Freescale Semiconductor Table 3-2. Instruction Set (Sheet Addressing Instruction Mode Opcode Operand INH 1B INH 3A INH IMM 89 ii ...
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... Freescale Semiconductor ∆ ∆ ∆ ∆ ∆ ∆ ∆ 0 — ∆ 0 — ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ...
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... Accumulator B 0 ⇒ V CLV Clear Overflow Flag CMPA (opr) Compare – M Memory CMPB (opr) Compare – M Memory $FF – M ⇒ M COM (opr) Ones Complement Memory Byte Freescale Semiconductor Table 3-2. Instruction Set (Sheet Addressing Instruction Mode Opcode Operand B IMM DIR EXT F5 hh ...
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... Freescale Semiconductor ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ — ∆ ∆ ...
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... C b7 LSLD Logical Shift Left Double LSR (opr) Logical Shift Right 0 b7 LSRA Logical Shift Right LSRB Logical Shift Right Freescale Semiconductor Table 3-2. Instruction Set (Sheet Addressing Instruction Mode Opcode Operand INH 08 INH 18 08 EXT 7E hh IND IND DIR 9D dd ...
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... Freescale Semiconductor ∆ ∆ ∆ ∆ — — ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ — — — ∆ 0 — ...
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... Memory from B D – ⇒ D SUBD (opr) Subtract Memory from D SWI Software See Figure 3-2 Interrupt A ⇒ B TAB Transfer ⇒ CCR TAP Transfer Register Freescale Semiconductor Table 3-2. Instruction Set (Sheet Addressing Instruction Mode Opcode Operand INH 39 INH 10 A IMM DIR 92 dd ...
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... Condition Codes — Bit not changed 0 Bit always cleared 1 Bit always set ∆ Bit cleared or set, depending on operation ↓ Bit can be cleared, cannot become set Freescale Semiconductor ∆ 0 — — — — — — — ∆ ∆ ...
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... Protected control bits (CR1 and CR0) in the configuration options register (OPTION) allow the user to select one of the four COP timeout rates. relationship between CR1 and CR0 and the COP timeout period for various system clock frequencies. Freescale Semiconductor DD MC68HC711D3 Data Sheet, Rev. 2.1 ...
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... Bit 4 Bit MC68HC711D3 Data Sheet, Rev. 2.1 XTAL = XTAL = 4.0 MHz 3.6864 MHz Time Out Time Out –0/+32.8 ms –0/+35.6 ms 32.768 ms 35.556 ms 131.07 ms 142.22 ms 524.29 ms 568.89 ms 2.1 sec 2.276 ms 1.0 MHz 921.6 kHz 2 1 Bit 0 Bit 2 Bit 1 Bit Freescale Semiconductor ...
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... All the on-chip (hardware) interrupts are individually maskable by local control bits. The software interrupt is non-maskable. The external input to the XIRQ pin is considered a non-maskable interrupt because it cannot be masked by software once it is enabled. However masked during reset and upon receipt of an interrupt at the XIRQ pin. Illegal opcode is also a non-maskable interrupt. Freescale Semiconductor ...
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... SPIE I bit PAII I bit PAOVI I bit TOI I bit I4/O5I I bit OC4I I bit OC3I I bit OC2I I bit OC1I I bit IC3I I bit IC2I I bit IC1I I bit RTII I bit None X bit None None None None None None NOCOP None CME None None Freescale Semiconductor ...
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... Since the operation of the I bit related interrupt structure has no effect on the X bit, the internal XIRQ pin remains effectively non-masked. In the interrupt priority logic, the XIRQ interrupt is a higher priority than any source that is maskable by the I bit. All I bit related interrupts operate normally with their own priority relationship. Freescale Semiconductor STACK SP PCL — ...
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... SCI interrupt block of sources within the SCI subsystem. 52 illustrate the interrupt process as it relates to normal processing. Figure 4-4 and shows how interrupt priority is resolved. Figure 4-4 and shows the resolution of interrupt MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
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... POWER-ON RESET (POR) DELAY 4064 E CYCLES LOAD PROGRAM COUNTER WITH CONTENTS OF $FFFE, $FFFF (VECTOR FETCH) Figure 4-4. Processing Flow Out of Reset (Sheet Freescale Semiconductor EXTERNAL RESET CLOCK MONITOR FAIL (WITH CME = 1) LOAD PROGRAM COUNTER WITH CONTENTS OF $FFFC, $FFFD (VECTOR FETCH) SET BITS S, I, AND X ...
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... RESTORE CPU REGISTERS EXECUTE THIS FROM STACK INSTRUCTION START NEXT INSTRUCTION 1A SEQUENCE MC68HC711D3 Data Sheet, Rev. 2.1 STACK CPU REGISTERS STACK CPU REGISTERS N INTERRUPT YET? Y SET I BIT RESOLVE INTERRUPT PRIORITY AND FETCH VECTOR FOR HIGHEST PENDING SOURCE SEE Figure 4-5 Freescale Semiconductor ...
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... BEGIN X BIT IN CCR SET ? N HIGHEST PRIORITY INTERRUPT ? N IRQ ? N RTII = IC1I = IC2I = IC3I = OC1I = Figure 4-5. Interrupt Priority Resolution (Sheet Freescale Semiconductor Y Y XIRQ PIN LOW ? REAL-TIME INTERRUPT ? TIMER IC1F ? TIMER IC2F ? TIMER IC3F ? TIMER OC1F ? N MC68HC711D3 Data Sheet, Rev. 2.1 Interrupts ...
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... N Y FLAG FETCH VECTOR PAOVF = 1 $FFDC, $FFDD N Y FLAG FETCH VECTOR PAIF = 1? $FFDA, $FFDB N FLAGS Y FETCH VECTOR SPIF = 1? OR $FFD8, $FFD9 MODF = 1? N FETCH VECTOR $FFD6, $FFD7 FETCH VECTOR $FFF2, $FFF3 MC68HC711D3 Data Sheet, Rev. 2.1 2B END Freescale Semiconductor ...
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... BEGIN Y FLAG RDRF = TDRE = IDLE = VALID SCI REQUEST Figure 4-6. Interrupt Source Resolution within SCI Freescale Semiconductor Y RIE = TIE = 1? N TCIE = 1? Y ILIE = 1? N MC68HC711D3 Data Sheet, Rev. 2.1 Interrupts YES VALID SCI REQUEST 57 ...
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... E clock driven out of the chip SMOD MDA IRVNE PSEL3 Note 1 0 Table 4-3. and Miscellaneous Register (HPRIO) Mode MODA 0 Single chip 1 Expanded multiplexed 0 Special bootstrap 1 Special test MC68HC711D3 Data Sheet, Rev. 2 Bit 0 PSEL2 PSEL1 PSEL0 Table 4-3. Latched at Reset SMOD MDA Freescale Semiconductor ...
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... During reset, PSEL3–PSEL0 are initialized to 0101, which corresponds to reserved (default to IRQ). IRQ becomes the highest priority I bit related interrupt source. Table 4-4. Highest Priority Interrupt Selection PSEL3–PSEL0 Freescale Semiconductor IRVNE E Clock IRV Out Out Out of Reset of Reset of Reset 0 On Off 0 On Off 0 On Off 1 ...
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... It also depends upon the circuitry connected to the MCU pins, and upon subsystems such as the timer, serial peripheral interface (SPI), or serial communications interface (SCI) that were or were not active when the wait mode was entered. 60 MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
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... Address: $0000 Bit 7 Read: PA7 Write: Reset: Hi-Z Alt. Func.: PAI And/Or: OC1 1. This pin is not bonded in the 40-pin version. Figure 5-1. Port A Data Register (PORTA) Freescale Semiconductor Functions (1) (1) PA6 PA5 PA4 PA3 ...
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... DDB7–DDB0 — Data Direction Bits for Port Corresponding port B pin configured as output 0 = Corresponding port B pin configured for input only PB6 PB5 PB4 PB3 A14 A13 A12 A11 DDB6 DDB5 DDB4 DDB3 MC68HC711D3 Data Sheet, Rev. 2 Bit 0 PB2 PB1 PB0 A10 Bit 0 DDB2 DDB1 DDB0 Freescale Semiconductor ...
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... Port C Data Direction Register Address: $0007 Bit 7 Read: DDC7 Write: Reset: 0 Figure 5-6. Data Direction Register for Port C (DDRC) DDC7–DDC0 — Data Direction Bits for Port Corresponding port C pin is configured as output 0 = Corresponding port C pin is configured for input only Freescale Semiconductor CWOM ...
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... DDRD bits 2, 3, and 4. If the SPI expects port D bits 2, 3, and outputs, they are outputs only if DDRD bits 2, 3, and 4 are set PD6 PD5 PD4 PD3 DDD6 DDD5 DDD4 DDD3 MC68HC711D3 Data Sheet, Rev. 2 Bit 0 PD2 PD1 PD0 Bit 0 DDD2 DDD1 DDD0 Freescale Semiconductor ...
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... SCDR. An advanced data recovery scheme distinguishes valid data from noise in the serial data stream. The data input is selectively sampled to detect receive data, and a majority voting circuit determines the value and integrity of each bit. Freescale Semiconductor MC68HC711D3 Data Sheet, Rev. 2.1 Figure ...
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... Figure 6-1. SCI Transmitter Block Diagram 66 (WRITE ONLY) FORCE PIN DIRECTION (OUT) TRANSMITTER CONTROL LOGIC SCSR INTERRUPT STATUS TDRE TIE TC TCIE SCCR2 SCI CONTROL 2 MC68HC711D3 Data Sheet, Rev. 2.1 DDD1 PIN BUFFER PD1 AND CONTROL TxD INTERNAL DATA BUS Freescale Semiconductor ...
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... BAUD RATE CLOCK DDD0 PIN BUFFER PD0 RxD AND CONTROL DISABLE DRIVER SCCR1 SCI CONTROL 1 SCI Tx SCI INTERRUPT REQUESTS REQUEST Freescale Semiconductor ÷16 DATA RECOVERY RE M WAKEUP LOGIC SCSR SCI STATUS 1 RDRF RIE IDLE ILIE OR RIE SCCR2 SCI CONTROL 2 Figure 6-2. SCI Receiver Block Diagram MC68HC711D3 Data Sheet, Rev ...
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... This type of wakeup allows messages to include gaps of idle time, unlike the idle-line method, but there is a loss of efficiency because of the extra bit time for each character (address bit) required for all characters. 68 MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
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... Reads access the receive data buffer and writes access the transmit data buffer. Receive and transmit are double buffered. Address: $002F Bit 7 Read: R7/T7 Write: Reset: Freescale Semiconductor R6/T6 R5/T5 R4/T4 R3/T3 Unaffected by reset Figure 6-3 ...
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... SCI interrupt requested when TC status flag is set RIE — Receiver Interrupt Enable Bit 0 = RDRF and OR interrupts disabled 1 = SCI interrupt requested when RDRF flag or the OR status flag is set WAKE TCIE RIE ILIE MC68HC711D3 Data Sheet, Rev. 2 Bit Bit 0 RE RWU SBK Freescale Semiconductor ...
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... Transmitter busy 1 = Transmitter idle RDRF — Receive Data Register Full Flag This flag is set if a received character is ready to be read from SCDR. Clear the RDRF flag by reading SCSR with RDRF set and then reading SCDR SCDR empty 1 = SCDR full Freescale Semiconductor RDRF ...
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... Bit 7 Read: TCLR Write: Reset Unaffected TCLR — Clear Baud Rate Counters (Test) RCKB — SCI Baud Rate Clock Check (Test SCP1 SCP0 RCKB Figure 6-7. Baud Rate Register (BAUD) MC68HC711D3 Data Sheet, Rev. 2 Bit 0 SCR2 SCR1 SCR0 Freescale Semiconductor ...
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... SCI baud rate timing chain. The prescale select bits determine the highest baud rate. The rate select bits determine additional divide by two stages to arrive at the receiver timing (RT) clock rate. The baud rate clock is the result of dividing the RT clock by 16. Freescale Semiconductor Table 6-1. Baud Rate Prescale Selects Crystal Frequency in MHz Divide 4 ...
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... Figure 6-8. SCI Baud Rate Diagram MC68HC711D3 Data Sheet, Rev. 2.1 INTERNAL BUS CLOCK (PH2) ÷ 4 ÷ 13 SCP1 AND SCP0 1:0 1:1 ÷ 16 SCI TRANSMIT BAUD RATE (1X) SCI RECEIVE BAUD RATE (16X) Freescale Semiconductor ...
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... The IDLE flag is set only after the RxD line has been busy and becomes idle, which prevents repeated interrupts for the whole time RxD remains idle. Freescale Semiconductor Figure 6-9, which shows SCI interrupt arbitration. ...
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... Serial Communications Interface (SCI) BEGIN Y FLAG RDRF = TDRE = IDLE = VALID SCI REQUEST Figure 6-9. Interrupt Source Resolution within SCI 76 Y RIE = TIE = TCIE = ILIE = 1? N MC68HC711D3 Data Sheet, Rev. 2 VALID SCI REQUEST Freescale Semiconductor ...
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... SPI device; slave devices that are not selected do not interfere with SPI bus activities master SPI device, the select line can optionally be used to indicate a multiple master bus contention. Refer to Figure 7-2. Freescale Semiconductor MC68HC711D3 Data Sheet, Rev. 2.1 77 ...
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... MSB LSB 8-BIT SHIFT REGISTER READ DATA BUFFER CLOCK CLOCK LOGIC MSTR SPE SPI CONTROL REGISTER 8 INTERNAL DATA BUS Figure 7-1. SPI Block Diagram MC68HC711D3 Data Sheet, Rev. 2.1 MISO S PD2 M S MOSI PD3 M M SCK PD4 S SS PD5 Freescale Semiconductor ...
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... Slave select (SS) 7.5.1 Master In/Slave Out (MISO) MISO is one of two unidirectional serial data signals input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. Freescale Semiconductor ...
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... Other precautions may need to be taken to prevent driver damage. If two devices are made masters at the same time, mode fault does not help protect either one unless one of them selects the other as slave. The amount of damage possible depends on the length of time both devices attempt to act as master. 80 MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
Page 81
... SPE — Serial Peripheral System Enable Bit 0 = SPI off 1 = SPI on DWOM — Port D Wired-OR Mode Bit DWOM affects all six port D pins Normal CMOS outputs 1 = Open-drain outputs MSTR — Master Mode Select Bit 0 = Slave mode 1 = Master mode Freescale Semiconductor SPE DWOM MSTR CPOL 0 ...
Page 82
... WCOL 0 MODF Figure 7-4. SPI Status Register (SPSR) and 7.6 SPI System Errors. MC68HC711D3 Data Sheet, Rev. 2.1 Figure 7-2 Figure 7-2 Frequency at 1.0 MHz 500 kHz 125 kHz 62.5 kHz 2 1 Bit Errors. 7.5.4 Slave Freescale Semiconductor and 7.4 ...
Page 83
... SPIF must be cleared by the time a second transfer of data from the shift register to the read buffer is initiated. Address: $002A Bit 7 Read: Bit 7 Write: Reset: Figure 7-5. SPI Data I/O Register (SPDR) SPI is double buffered in and single buffered out. Freescale Semiconductor Bit 6 Bit 5 Bit 4 Bit 3 Unaffected by reset NOTE MC68HC711D3 Data Sheet, Rev ...
Page 84
... Serial Peripheral Interface (SPI) 84 MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
Page 85
... If the COP is allowed to time out, a reset is generated, which drives the RESET pin low to reset the MCU and the external system. Refer to Table 8-1 Freescale Semiconductor tapped off of the free-running counter chain. The COP for crystal related frequencies and periods. ...
Page 86
... TOF FF1 CLEAR COP SYSTEM TIMER RESET Figure 8-1. Timer Clock Divider Chains MC68HC711D3 Data Sheet, Rev. 2 CLOCK INTERNAL BUS CLOCK (PH2) SPI SCI RECEIVER CLOCK ÷16 SCI TRANSMIT CLOCK PULSE ACCUMULATOR REAL-TIME INTERRUPT FF2 Q S FORCE R COP Q RESET Freescale Semiconductor ...
Page 87
... Because these delays offset each other when the time between two edges is being measured, the delay can be ignored. When an input capture is being used with an output compare, there is a similar delay between the actual compare point and when the output pin changes state. Freescale Semiconductor Table 8-1. Timer Summary XTAL Frequencies 4 ...
Page 88
... BY I BIT IN CCR) TO PULSE ACCUMULATOR OC1I 8 BIT 7 OC2I 7 BIT 6 OC3I 6 BIT 5 OC4I 5 BIT 4 I4/O5I 4 BIT 3 IC1I 3 BIT 2 IC2I 2 BIT 1 IC3I 1 BIT 0 TMSK 1 PORT A PIN CONTROL Freescale Semiconductor PORT A PINS PA7/OC1/ PAI PA6/OC2/ OC1 PA5/OC3/ OC1 PA4/OC4/ OC1 PA3/IC4/ OC5/OC1 PA2/IC1 PA1/IC2 PA0/IC3 ...
Page 89
... Address: $0010 — TIC1 (High) Bit 15 Read: Bit 15 Write: Reset: = Unimplemented Figure 8-4. Timer Input Capture Registers (TICx) Freescale Semiconductor EDG4A EDG1B EDG1A EDG2B 0 ...
Page 90
... Compare 5 Register (TI4/O5) MC68HC711D3 Data Sheet, Rev. 2 Bit 0 Bit 2 Bit 1 Bit Bit 8 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Bit 8 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit 0 8.7 Pulse Accumulator Bit 8 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Freescale Semiconductor ...
Page 91
... However, if coherency is not needed, byte accesses can be used. For output compare functions, write a comparison value to output compare registers TOC1–TOC4 and TI4/O5. When TCNT value matches the comparison value, specified pin actions occur. Freescale Semiconductor MC68HC711D3 Data Sheet, Rev. 2.1 Output Compare (OC) ...
Page 92
... Bit 5 Bit 4 Bit MC68HC711D3 Data Sheet, Rev. 2 Bit 8 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Bit 8 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Bit 8 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Bit 8 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Freescale Semiconductor ...
Page 93
... Figure 8-8. Output Compare 1 Mask Register (OC1M) OC1M7–OC1M3 — Output Compare Masks 0 = OC1 disabled 1 = OC1 enabled to control the corresponding pin of port A Bits 2–0 — Not implemented; always read 0. Set bit(s) to enable OC1 to control corresponding pin(s) of port A. Freescale Semiconductor FOC2 FOC3 ...
Page 94
... Bit 7 Write: Reset Unimplemented Figure 8-10. Timer Counter Registers (TCNT) In normal modes, TCNT is read-only OC1D6 OC1D5 OC1D4 OC1D3 Bit 14 Bit 13 Bit 12 Bit Bit 6 Bit 5 Bit 4 Bit MC68HC711D3 Data Sheet, Rev. 2 Bit Bit 8 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Freescale Semiconductor ...
Page 95
... IC1I–IC3I — Input Capture x Interrupt Enable Bits If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence is requested. Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in TMSK1 enable the corresponding interrupt sources. Freescale Semiconductor ...
Page 96
... Pulse Accumulator. Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2 enable the corresponding interrupt sources OC2F OC3F OC4F I4/O5F RTII PAOVI PAII NOTE MC68HC711D3 Data Sheet, Rev. 2 Bit 0 IC1F IC2F IC3F Bit 0 0 PR1 PR0 Freescale Semiconductor ...
Page 97
... Interrupt. PAOVF — Pulse Accumulator Overflow Interrupt Flag Refer to 8.7 Pulse Accumulator. PAIF — Pulse Accumulator Input Edge Interrupt Flag Refer to 8.7 Pulse Accumulator. Bits 3–0 — Not implemented Always read 0. Freescale Semiconductor Table 8-4. Timer Prescale PR1 and PR0 Prescaler ...
Page 98
... MHz MHz 2.731 ms 4.096 ms 5.461 ms 8.192 ms 10.923 ms 16.384 ms 21.845 ms 32.768 RTII PAOVI PAII (OC). MC68HC711D3 Data Sheet, Rev. 2.1 Table 8-5 for the periodic MHz MHz 13 (E/2 ) 8.192 ms 14 16.384 ms (E/2 ) 32.768 ms 15 (E/2 ) 65.536 Bit 0 0 PR1 PR0 Freescale Semiconductor ...
Page 99
... Bit DDRA3 determines whether port A bit three is an input or an output when used for general-purpose I/O. The remaining bits control the pulse accumulator. Address: $0026 Bit 7 Read: DDRA7 Write: Reset: 0 Figure 8-18. Pulse Accumulator Control Register (PACTL) Freescale Semiconductor NOTE RTIF PAOVF PAIF 0 0 ...
Page 100
... Figure 8-19. 8-7. The pulse accumulator counter can be read or written at any time. MC68HC711D3 Data Sheet, Rev. 2.1 Table 8- MHz MHz 13 (E/2 ) 8.192 ms 14 16.384 ms (E/2 ) 32.768 ms 15 (E/2 ) 65.536 ms 16 (E/2 ) Chapter 4 Resets, Interrupts, and Freescale Semiconductor ...
Page 101
... BUFFER MAIN TIMER OC1 PACTL CONTROL Table 8-7. Pulse Accumulator Timing in Gated Mode CPU Clock Cycle Time 6 (E (E/2 ) Freescale Semiconductor TMSK2 INT ENABLES 2:1 MUX Figure 8-19. Pulse Accumulator Common XTAL Frequencies Selected Crystal 4.0 MHz (E) 1.0 MHz (1/E) 1000 ns 1 count - 64.0 µ ...
Page 102
... PAMOD PEDGE DDRA3 NOTE for more information. PEDGE Action on Clock 0 PAI falling edge increments the counter. 1 PAI rising edge increments the counter PAI inhibits counting PAI inhibits counting. Ports. MC68HC711D3 Data Sheet, Rev. 2 Bit 0 I4/O5 RTR1 RTR0 Table 8-8. Freescale Semiconductor ...
Page 103
... PAIF by writing to the TFLG register. Address: $0024 Bit 7 Read: TOI Write: Reset: 0 Figure 8-22. Timer Interrupt Mask 2 Register (TMSK2) Address: $0025 Bit 7 Read: TOF Write: Reset: 0 Figure 8-23. Timer Interrupt Flag 2 Register (TFLG2) Freescale Semiconductor Bit 6 Bit 5 Bit 4 Bit 3 Unaffected by reset RTII PAOVI PAII 0 0 ...
Page 104
... Programmable Timer 104 MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
Page 105
... For proper operation recommended that V ≤ Out inputs are connected to an appropriate logic voltage level (for example, either Freescale Semiconductor NOTE for guaranteed operating NOTE and V be constrained to the range In Out ) ≤ Reliability of operation is enhanced if unused DD ). MC68HC711D3 Data Sheet, Rev. 2.1 ...
Page 106
... MC68HC711D3 Data Sheet, Rev. 2.1 Symbol Value –40 to +85 A –40 to +105 Symbol Value + (P × Θ User-determined A 50 Θ INT I 273° × INT User-determined I/O × 273° Θ × (at equilibrium). Use this value D Freescale Semiconductor Unit °C Unit °C °C °C W/°C ...
Page 107
... RESET and MODA is not applicable because they are open-drain pins applicable to ports C and D in wired-OR mode. 3. All ports configured as inputs 476.5 ns. cyc Freescale Semiconductor (1) All outputs All outputs except RESET, EXTAL, and MODA All outputs except XTAL All inputs except RESET RESET ...
Page 108
... SPEC 70 20 SPEC TIMING 70 20 points. Figure 9-2. Test Methods MC68HC711D3 Data Sheet, Rev. 2.1 ( 3. 3.26 K 2.38 K 200 pF V – 0 NOM SPEC (NOTE 1) V – 0 0.4 V – 0.8 volts while timing measurements are taken Freescale Semiconductor ...
Page 109
... Refer to Input/Output (I/O) Ports for further details. (1) PA0–PA3 (2) PA0–PA3 (1) (3) PA7 PW (2) (3) PA7 Notes: 1. Rising edge sensitive input 2. Falling edge sensitive input 3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2. Freescale Semiconductor (1) Symbol cyc f XTAL cyc PCSU PW ...
Page 110
V DD EXTAL 4064 t cyc E RESET MODA, MODB FFFE FFFE FFFE ADDRESS Figure 9-4. POR and External Reset Timing Diagram t PCSU PW RSTL t MPS NEW FFFE FFFF FFFE FFFE FFFE PC t MPH NEW FFFE FFFE ...
Page 111
RESET (1) IRQ PW IRQ (2) IRQ or XIRQ t STOPDELAY AS E STOP STOP (4) ADDRESS ADDR ADDR + 1 STOP STOP (5) ADDRESS ADDR ADDR + 1 Notes: 1. Edge sensitive IRQ pin (IRQE bit = 1) 2. ...
Page 112
E IRQ, XIRQ, OR INTERNAL INTERRUPTS WAIT WAIT SP SP – 1 ADDRESS ADDR ADDR + 1 PCL PCH, YL, YH, XL, XH CCR STACK REGISTERS R/W Note: RESET also causes recovery from WAIT. Figure 9-6. WAIT Recovery ...
Page 113
E t PCSU (1) IRQ PW IRQ (2) IRQ , XIRQ OR INTERNAL INTERRUPT NEXT ADDRESS NEXT OPCODE AS OP ADDRESS — — PCL CODE R/W Notes: 1. Edge sensitive IRQ pin (IRQE bit = 1) ...
Page 114
... V , unless DD DD NEW DATA VALID t PWD NEW DATA VALID t PDH Freescale Semiconductor Unit MHz ...
Page 115
... To recalculate the approximate bus timing values, substitute the following expressions in place of 1 the above formulas, where applicable: CYC (a) (1-dc) × 1/4 t CYC (b) dc × 1/4 t CYC Where the decimal value of duty cycle percentage (high time). 3. Formula only for MHz. Freescale Semiconductor (1) Symbol — cyc – cyc – 29.5 ns cyc ...
Page 116
... Electrical Characteristics E R/W, ADDRESS (NON-MUX) 36 READ ADDRESS/DATA (MULTIPLEXED) WRITE Note: Measurement points shown are 20% and 70 Figure 9-10. Multiplexed Expansion Bus Timing Diagram 116 ADDRESS 19 ADDRESS MC68HC711D3 Data Sheet, Rev. 2 DATA 21 DATA Freescale Semiconductor ...
Page 117
... Fall time (70 20 SPI outputs (SCK, MOSI, and MISO) SPI inputs (SCK, MOSI, MISO, and SS 5.0 Vdc ± 10 Vdc otherwise noted. 2. Signal production depends on software. 3. Assumes 200 pF load on all SPI pins. Freescale Semiconductor (1) ( 200 pF 200 pF All timing is shown with respect to 20 MC68HC711D3 Data Sheet, Rev ...
Page 118
... SS IS HELD HIGH ON MASTER MSB IN BIT MASTER MSB OUT BIT HELD HIGH ON MASTER MSB IN BIT MASTER MSB OUT BIT MC68HC711D3 Data Sheet, Rev. 2 LSB IN 11 (REF) 10 MASTER LSB OUT 12 12 SEE NOTE 13 SEE NOTE 6 7 LSB IN 11 (REF) 10 MASTER LSB OUT 12 Freescale Semiconductor ...
Page 119
... Figure 9-13. SPI Slave Timing (CPHA = 0) SS (INPUT) SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 SEE MISO NOTE (OUTPUT) MOSI (INPUT) Note: Not defined but normally LSB of character previously transmitted Figure 9-14. SPI Slave Timing (CPHA = 1) Freescale Semiconductor BIT MSB OUT BIT MSB ...
Page 120
... Electrical Characteristics 120 MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
Page 121
... Ordering Information Package Type 40-pin DIP 44-pin PLCC 44-pin QFP 10.3 40-Pin DIP (Case 711-03 Freescale Semiconductor Table 10-1. MC Order Numbers MC Order Number Temperature 2 MHz –40 to +85°C MC68HC711D3CP2 –40 to +85°C MC68HC711D3CFN2 –40 to +105°C MC68HC711D3VFN2 –40 to +85°C ...
Page 122
... BSC 0.032 0.66 0.81 0.51 0.64 0.656 16.51 16.66 0.656 16.51 16.66 0.048 1.07 1.21 0.048 1.07 1.21 0.056 1.07 1.42 0.020 0.50 10° 2° 10° 0.630 15.50 16.00 1.02 Freescale Semiconductor ...
Page 123
... QFP (Case 824A-01 - -D- A 0.20 (0.008) M 0.05 (0.002) A-B 0.20 (0.008 -C- H SEATING G PLANE DATUM -H- PLANE W DETAIL C Freescale Semiconductor -B- DETAIL A A DETAIL C DATUM -H- PLANE 0.01 (0.004 MC68HC711D3 Data Sheet, Rev. 2.1 44-Pin QFP (Case 824A-01 -A-, -B-, -D- DETAIL A F BASE METAL ...
Page 124
... Ordering Information and Mechanical Specifications 124 MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
Page 125
... One software-selectable channel • 32 input/output (I/O) pins: – 26 bidirectional I/O pins – 3 input-only pins – 3 output-only pins • Available in these packages: – 44-pin plastic leaded chip carrier (PLCC) – 44-pin quad flat pack (QFP) Freescale Semiconductor MC68HC711D3 Data Sheet, Rev. 2.1 125 ...
Page 126
... PERIODIC INTERRUPT MC68HC11D3 CPU CORE DATA DIRECTION REGISTER C PORT C MC68HC711D3 Data Sheet, Rev. 2.1 E MC68HC11D3 — 4 KBYTES ROM MC68HC11D0 — 0 BYTES ROM 192 BYTES RAM SERIAL PERIPHERAL COMMUNICATIONS INTERFACE INTERFACE (SPI) TxD DATA DIRECTION REGISTER D PORT D Freescale Semiconductor SERIAL (SCI) RxD ...
Page 127
... A.3 Pin Assignments PC4/A4/D4 PC5/A5/D5 PC6/A6/D6 PC7/A7/D7 XIRQ PD7/R/W PD6/AS RESET IRQ PD0/RxD PD1/TxD Figure A-2. Pin Assignments for 44-Pin PLCC XIRQ RESET Figure A-3. Pin Assignments for 44-Pin QFP Freescale Semiconductor PC4 1 PC5 2 PC6 3 4 PC7 5 6 PD7 7 PD6 8 9 IRQ ...
Page 128
... KBYTES ROM (MC68HC11D3) PRESENT AT RESET AND CAN BE DISABLED BY ROM ON BIT IN CONFIG REGISTER. INTERRUPT VECTORS ARE EXTERNAL. BOOT $BFC0 ROM SPECIAL MODES INTERRUPT $BFFF VECTORS 4-KBYTES ROM $FFC0 NORMAL MODES INTERRUPT $FFFF VECTORS Value –40 to +85 Value Θ Freescale Semiconductor Unit °C Unit °C/W ...
Page 129
... A.6 Ordering Information MCU Package MC68HC11D3 44-pin PLCC (Custom ROM) 44-pin PLCC MC68HC11D0 (No ROM) 44-pin QFP Freescale Semiconductor MC Order Number Temperature 2 MHz –40 to +85°C MC68HC11D3CFN2 –40 to +85°C MC68HC11D0CFN2 –40 to +85°C MC68HC11D0CFB2 MC68HC711D3 Data Sheet, Rev. 2.1 Ordering Information ...
Page 130
... MC68HC11D3 and MC68HC11D0 130 MC68HC711D3 Data Sheet, Rev. 2.1 Freescale Semiconductor ...
Page 131
... I = – 0.8 mA 4.5 V Load DD Output low voltage All outputs except XTAL I = 1.6 mA 5.0 V Load 1.0 mA 3.0 V Load DD Freescale Semiconductor MC68HC11D0) in all aspects other than electrical apply to the MC68L11D0 with the exceptions Symbol T (1) Symbol The dc electrical table continues on next page. MC68HC711D3 Data Sheet, Rev. 2.1 ...
Page 132
... IDD unless otherwise noted MC68HC711D3 Data Sheet, Rev. 2.1 Min Max – 0.3 0 — ±10 — ±1 In — ± — 10 — — 12 — — 100 1 2 150 21 42 specification is not OH Freescale Semiconductor Unit V V µA µA V µ µA mW ...
Page 133
... MCU write to port A MCU writes to ports B, C, and 1 150 ns PWD cyc 3 5.5 Vdc Vdc otherwise noted. 2. Port C and D timing is valid for active drive (CWOM and DWOM bits not set in PIOC and SPCR registers respectively). Freescale Semiconductor (1) Symbol cyc f XTAL PCSU PW RSTL ...
Page 134
... AVM 150 — 25 ASL 95 — 33 AHL 120 — 58 ASD 220 — 95 ASH 120 — 58 735 — 298 — 440 — 150 — 88 MAD and 70 Freescale Semiconductor Unit 2.0 MHz — ns — ns — — ns — ns — 133 ns — ns — ns — ns — ns — ...
Page 135
... Fall time (70 20 SPI outputs (SCK, MOSI, and MISO) SPI inputs (SCK, MOSI, MISO, and SS 3.0 Vdc to 5.5 Vdc Vdc otherwise noted. 2. Signal production depends on software. 3. Assumes 100 pF load on all SPI pins. Freescale Semiconductor (1) Symbol f op(m) f op(s) t cyc(m) t CYC(s) t lead(m) t lead(s) ...
Page 136
... MC68L11D0 B.3 Ordering Information Package 44-pin PLCC 44-pin QFP 136 Frequency Features 2 MHz No ROM MC68L11D0FN2 2 MHz No ROM MC68L11D0FB2 MC68HC711D3 Data Sheet, Rev. 2.1 MC Order Number Freescale Semiconductor ...
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...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...