MC68HC711D3CFNE3 Freescale Semiconductor, MC68HC711D3CFNE3 Datasheet - Page 67

• Manufacturer Part Number: MC68HC711D3CFNE3
• Description: IC MCU 8BIT 2MHZ 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711D3CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 26
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

7.1 Data Format
7.2 Transmit Operation
TECHNICAL DATA
The serial communications interface (SCI) is a universal asynchronous receiver trans-
mitter (UART), one of two independent serial I/O subsystems in the MC68HC11D3. It
has a standard nonreturn to zero (NRZ) format (one start, eight or nine data, and one
stop bit). Several baud rates are available. The SCI transmitter and receiver are inde-
pendent, but use the same data format and bit rate.
The serial data format requires the following conditions:
Selection of the word length is controlled by the M bit of SCI control register SCCR1.
The SCI transmitter includes a parallel transmit data register (SCDR) and a serial shift
register. The contents of the serial shift register can only be written through the SCDR.
This double buffered operation allows a character to be shifted out serially while an-
other character is waiting in the SCDR to be transferred into the serial shift register.
The output of the serial shift register is applied to TxD as long as transmission is in
progress or the transmit enable (TE) bit of serial communication control register 2
(SCCR2) is set. The block diagram, Figure 7-1, shows the transmit serial shift register,
and the buffer logic at the top of the figure.
1. An idle line in the high state before transmission or reception of a message
2. A start bit, logic zero, transmitted or received, that indicates the start of each
3. Data that is transmitted and received least significant bit (LSB) first
4. A stop bit, logic one, used to indicate the end of a frame (A frame consists of a
5. A break (defined as the transmission or reception of a logic zero for some mul-
character
start bit, a character of eight or nine data bits, and a stop bit.)
tiple number of frames).
SERIAL COMMUNICATIONS INTERFACE
Freescale Semiconductor, Inc.
For More Information On This Product,
SERIAL COMMUNICATIONS INTERFACE
Go to: www.freescale.com
SECTION 7
7-1