MC68HC705C9ACFBE Freescale Semiconductor, MC68HC705C9ACFBE Datasheet - Page 16

• Manufacturer Part Number: MC68HC705C9ACFBE
• Description: IC MCU 8BIT 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705C9ACFBE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 352 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Processor Series: HC705C
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 352 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 31
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Package: 44PQFP
• Family Name: HC05
• Maximum Speed: 2.1 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

General Description
1.4 Mask Options
The following two mask option registers are used to select features controlled by mask changes on the
MC68HC05C9A and the MC68HC05C12A:
The mask option registers are EPROM locations which must be programmed prior to operation of the
microcontroller.
1.4.1 Port B Mask Option Register (PBMOR)
The PBMOR register, shown in
each port B bit (when in input mode) has the pullup and interrupt enabled. The port B interrupts share the
vector and edge/edge-level sensitivity with the IRQ pin. For more details, (see
or Port
1.4.2 C12 Mask Option Register (C12MOR)
The C12MOR register, shown in
16
•
•
•
•
•
•
PBPU7–PBPU0 — Port B Pullup/Interrupt Enable Bits
•
•
•
•
1 = Pullup and CPU interrupt enabled
0 = Pullup and CPU interrupt disabled
The port D data direction register ($0007) is disabled and the seven port D pins become input only.
SPI output signals (MOSI, MISO, and SCK) do not require the data direction register control for
output capability.
The port D wire-OR mode control bit (bit 5 of SPCR $000A) is disabled, preventing open-drain
configuration of port D.
The RESET pin becomes input only.
Port B mask option register (PBMOR)
C12 mask option register (C12MOR)
Select between MC68HC05C9A/C12A configuration
Enable/disable stop mode (C12A mode only)
Enable/disable COP (C12A mode only)
Edge-triggered only or edge- and level-triggered external interrupt pin (IRQ pin) (C12A mode only).
B)).
The current capability of the port B pullup devices is equivalent to the
MC68HC05C9A, which is less than the MC68HC05C12A.
$3FF0
PBPU7
Bit 7
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
Figure 1-2. Port B Mask Option Register
PBPU6
Figure
Figure
6
1-2, contains eight programmable bits which determine whether
1-3, controls the following options:
PBPU5
5
NOTE
PBPU4
4
PBPU3
3
PBPU2
2
PBPU1
4.3 External Interrupt (IRQ
1
Freescale Semiconductor
PBPU0
Bit 0