HD64F3644H Renesas Electronics America, HD64F3644H Datasheet - Page 133

• Manufacturer Part Number: HD64F3644H
• Description: IC H8 MCU FLASH 32K 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644H

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Package: 64PQFP
• Family Name: H8
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 45
• Interface Type: SCI
• On-chip Adc: 8-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.4
6.4.1
Table 6.5 illustrates the principle of operation of the on-chip flash memory in the H8/3644F,
H8/3643F, and H8/3642AF.
Like EPROM, flash memory is programmed by applying a high gate-to-drain voltage that draws
hot electrons generated in the vicinity of the drain into a floating gate. The threshold voltage of a
programmed memory cell is therefore higher than that of an erased cell. Cells are erased by
grounding the gate and applying a high voltage to the source, causing the electrons stored in the
floating gate to tunnel out. After erasure, the threshold voltage drops. A memory cell is read like
an EPROM cell, by driving the gate to a high level and detecting the drain current, which depends
on the threshold voltage. Erasing must be done carefully, because if a memory cell is overerased,
its threshold voltage may become negative, causing the cell to operate incorrectly.
Section 6.7.6, Erase Flowcharts and Sample Programs, shows optimal erase control flowcharts and
sample programs.
Table 6.5
Memory
cell
Memory
array
Flash Memory Overview
Principle of Flash Memory Operation
Program
Principle of Memory Cell Operation
Vd
Vg = V
PP
0 V
Vd
V
0 V
0 V
PP
Erase
Vs = V
PP
Open
Open
Rev. 6.00 Sep 12, 2006 page 111 of 526
Open
0 V
V
0 V
PP
Read
Vd
REJ09B0326-0600
Vg = V
Section 6 ROM
CC
0 V
Vd
V
0 V
0 V
CC