HD64F3644H Renesas Electronics America, HD64F3644H Datasheet - Page 308

• Manufacturer Part Number: HD64F3644H
• Description: IC H8 MCU FLASH 32K 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644H

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Package: 64PQFP
• Family Name: H8
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 45
• Interface Type: SCI
• On-chip Adc: 8-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 10 Serial Communication Interface
6.
Simultaneous Transmit/Receive: A simultaneous transmit/receive operation is carried out as
follows.
1. Set bits SO1, SI1, and SCK1 to 1 in PMR3 to select the SO
2. Clear bit SNC1 in SCR1 to 0, set bit SNC0 to 0 or 1, and clear bit MRKON to 0, designating
3. Write transmit data in SDRL and SDRU, as follows.
4. Set the SCSR1 start flag (STF) to 1. SCI1 starts operating. Transmit data is output at pin SO
5. After data transmission and reception are complete, bit IRRS1 in IRR2 is set to 1.
6. Read the received data from SDRL and SDRU, as follows.
When an internal clock is used, a serial clock is output from pin SCK
transmit data. After data transmission is complete, the serial clock is not output until the next time
the start flag is set to 1. During this time, pin SO
transmitted.
When an external clock is used, data is transmitted and received in synchronization with the serial
clock input at pin SCK
the serial clock continues to be input; no data is transmitted or received and the SCSR1 overrun
error flag (bit ORER) is set to 1.
While transmission is stopped, the output value of pin SO
SCSR1.
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REJ09B0326-0600
necessary, set bit POF1 in PMR7 for NMOS open-drain output at pin SO
8- or 16-bit synchronous transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing
data to SCR1 when bit MRKON in SCR1 is cleared to 0 initializes the internal state of SCI1.
8-bit transfer mode:
16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
Receive data is input at pin SI
8-bit transfer mode:
16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
After data reception is complete, an overrun occurs if the serial clock continues to be input; no
data is received and the SCSR1 overrun error flag (bit ORER) is set to 1.
1
. After data transmission and reception are complete, an overrun occurs if
SDRL
SDRL
1
.
1
continues to output the value of the last bit
1
can be changed by rewriting bit SOL in
1
, SI
1
, and SCK
1
in synchronization with the
1
.
1
pin functions. If
1
.