HD64F3644H Renesas Electronics America, HD64F3644H Datasheet - Page 324

• Manufacturer Part Number: HD64F3644H
• Description: IC H8 MCU FLASH 32K 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644H

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Package: 64PQFP
• Family Name: H8
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 45
• Interface Type: SCI
• On-chip Adc: 8-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 10 Serial Communication Interface
Bit 4 Framing Error (FER): Bit 4 indicates that a framing error has occurred during reception
in asynchronous mode.
Bit 4: FER
0
1
Notes: 1. When bit RE in SCR3 is cleared to 0, bit FER is not affected and retains its previous
Bit 3 Parity Error (PER): Bit 3 indicates that a parity error has occurred during reception with
parity added in asynchronous mode.
Bit 3: PER
0
1
Notes: 1. When bit RE in SCR3 is cleared to 0, bit PER is not affected and retains its previous
Rev. 6.00 Sep 12, 2006 page 302 of 526
REJ09B0326-0600
2. Note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the
2. Receive data in which it a parity error has occurred is still transferred to RDR, but bit
state.
second stop bit is not checked. When a framing error occurs the receive data is
transferred to RDR but bit RDRF is not set. Reception cannot be continued with bit FER
set to 1. In synchronous mode, neither transmission nor reception is possible when bit
FER is set to 1.
state.
RDRF is not set. Reception cannot be continued with bit PER set to 1. In synchronous
mode, neither transmission nor reception is possible when bit PER is set to 1.
Description
Reception in progress or completed *
Clearing condition:
After reading FER = 1, cleared by writing 0 to FER
A framing error has occurred during reception *
Setting condition:
When the stop bit at the end of the receive data is checked for a value of 1 at
the end of reception, and the stop bit is 0 *
Reception in progress or completed *
Clearing condition:
After reading PER = 1, cleared by writing 0 to PER
A parity error has occurred during reception *
Setting condition:
When the number of 1 bits in the receive data plus parity bit does not match the
parity designated by bit PM in the serial mode register (SMR)
Description
1
1
2
2
2
(initial value)
(initial value)