HD64F3644H Renesas Electronics America, HD64F3644H Datasheet - Page 343

IC H8 MCU FLASH 32K 64-QFP

HD64F3644H

Manufacturer Part Number
HD64F3644H
Description
IC H8 MCU FLASH 32K 64-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet

Specifications of HD64F3644H

Core Processor
H8/300L
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Package
64PQFP
Family Name
H8
Maximum Speed
8 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
45
Interface Type
SCI
On-chip Adc
8-chx8-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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If no receive error is found in the above checks, bit RDRF is set to 1, and the receive data is stored
in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the error checks identify a
receive error, bit OER, PER, or FER is set to 1 depending on the kind of error. Bit RDRF retains
its state prior to receiving the data. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested.
Table 10.15 shows the conditions for detecting a receive error, and receive data processing.
Note: No further receive operations are possible while a receive error flag is set. Bits OER, FER,
Table 10.15 Receive Error Detection Conditions and Receive Data Processing
Receive Error
Overrun error
Framing error
Parity error
Figure 10.14 shows an example of the operation when receiving in asynchronous mode.
Serial
data
RDRF
FER
LSI
operation
User
processing
PER, and RDRF must therefore be cleared to 0 before resuming reception.
Figure 10.14 Example of Operation when Receiving in Asynchronous Mode
1
Start
bit
0
Abbreviation
FER
PER
OER
D0
D1
Receive
1 frame
data
D7
(8-Bit Data, Parity, 1 Stop Bit)
Detection Conditions
When the next date receive
operation is completed while bit
RDRF is still set to 1 in SSR
When the stop bit is 0
When the parity (odd or even)
set in SMR is different from that
of the received data
Parity
0/1
bit
RXI request
Stop
bit
1
Start
bit
0
D0
RDRF
cleared to 0
RDR data read
1 frame
Section 10 Serial Communication Interface
D1
Rev. 6.00 Sep 12, 2006 page 321 of 526
Receive
data
D7
Received Data Processing
Receive data is not transferred
from RSR to RDR
Receive data is transferred
from RSR to RDR
Receive data is transferred
from RSR to RDR
Parity
0/1
bit
Stop
bit
0
0 start bit
detected
Mark state
(idle state)
REJ09B0326-0600
1
ERI request in
response to
framing error
Framing error
processing

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