HD64F3644H Renesas Electronics America, HD64F3644H Datasheet - Page 359

• Manufacturer Part Number: HD64F3644H
• Description: IC H8 MCU FLASH 32K 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644H

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Package: 64PQFP
• Family Name: H8
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 45
• Interface Type: SCI
• On-chip Adc: 8-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

For further details, see section 3.3, Interrupts.
10.3.8
The following points should be noted when using SCI3.
1. Relation between writes to TDR and bit TDRE
2. Operation when a number of receive errors occur simultaneously
Table 10.17 SSR Status Flag States and Receive Data Transfer
RDRF * OER
1
0
0
1
1
0
1
Legend:
O: Receive data is transferred from RSR to RDR.
Note:
: Receive data is not transferred from RSR to RDR.
Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial
transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared
to 0 automatically. When SCI3 transfers data from TDR to TSR, bit TDRE is set to 1.
Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to
TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost of it has
not yet been transferred to TSR. Accordingly, to ensure that serial transmission is performed
dependably, you should first check that bit TDRE is set to 1, then write the transmit data to
TDR once only (not two or more times).
If a number of receive errors are detected simultaneously, the status flags in SSR will be set to
the states shown in table 10.17. If an overrun error is detected, data transfer from RSR to RDR
will not be performed, and the receive data will be lost.
SSR Status Flags
* Bit RDRF retains its state prior to data reception.
1
0
0
1
1
0
1
Application Notes
FER
0
1
0
1
0
1
1
PER
0
0
1
0
1
1
1
Receive Data Transfer
(RSR
O
O
O
RDR)
Section 10 Serial Communication Interface
Receive Error Status
Overrun error
Framing error
Parity error
Overrun error + framing error
Overrun error + parity error
Framing error + parity error
Overrun error + framing error + parity error
Rev. 6.00 Sep 12, 2006 page 337 of 526
REJ09B0326-0600