HD64F3644H Renesas Electronics America, HD64F3644H Datasheet - Page 362

• Manufacturer Part Number: HD64F3644H
• Description: IC H8 MCU FLASH 32K 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644H

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Package: 64PQFP
• Family Name: H8
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 45
• Interface Type: SCI
• On-chip Adc: 8-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 10 Serial Communication Interface
7. Relation between RDR reads and bit RDRF
Communication
line
RDRF
RDR
Rev. 6.00 Sep 12, 2006 page 340 of 526
REJ09B0326-0600
In a receive operation, SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0
when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1,
this indicates that an overrun error has occurred.
When the contents of RDR are read, bit RDRF is cleared to 0 automatically. Therefore, if bit
RDR is read more than once, the second and subsequent read operations will be performed
while bit RDRF is cleared to 0. Note that, when an RDR read is performed while bit RDRF is
cleared to 0, if the read operation coincides with completion of reception of a frame, the next
frame of data may be read. This is illustrated in figure 10.27.
In this case, only a single RDR read operation (not two or more) should be performed after
first checking that bit RDRF is set to 1. If two or more reads are performed, the data read the
first time should be transferred to RAM, etc., and the RAM contents used. Also, ensure that
there is sufficient margin in an RDR read operation before reception of the next frame is
completed. To be precise in terms of timing, the RDR read should be completed before bit 7 is
transferred in synchronous mode, or before the STOP bit is transferred in asynchronous mode.
Figure 10.27 Relation between RDR Read Timing and Data
Frame 1
Data 1
RDR read
Frame 2
Data 2
Data 1
(A)
RDR read
Data 1 is read at point
Data 2 is read at point
(B)
Frame 3
Data 3
Data 3
(B)
(A)