HD64F3644H Renesas Electronics America, HD64F3644H Datasheet - Page 366

• Manufacturer Part Number: HD64F3644H
• Description: IC H8 MCU FLASH 32K 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644H

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Package: 64PQFP
• Family Name: H8
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 45
• Interface Type: SCI
• On-chip Adc: 8-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 11 14-Bit PWM
Upon reset, PWDRU and PWDRL are initialized to H'C000.
11.3
When using the 14-bit PWM, set the registers in the following sequence.
1. Set bit PWM in port mode register 1 (PMR1) to 1 so that pin P1
2. Set bit PWCR0 in the PWM control register (PWCR) to select a conversion period of either
3. Set the output waveform data in PWM data registers U and L (PWDRU/L). Be sure to write in
Rev. 6.00 Sep 12, 2006 page 344 of 526
REJ09B0326-0600
output.
32,768/ (PWCR0 = 1) or 16,384/ (PWCR0 = 0).
the correct sequence, first PWDRL then PWDRU. When data is written to PWDRU, the data
in these registers will be latched in the PWM waveform generator, updating the PWM
waveform generation in synchronization with internal signals.
One conversion period consists of 64 pulses, as shown in figure 11.2. The total of the high-
level pulse widths during this period (T
This relation can be represented as follows.
where t is the PWM input clock period, either 2/ (bit PWCR0 = 0) or 4/ (bit PWCR0 = 1).
Example:
T
Operation
H
T = t
t
= (data value in PWDRU and PWDRL + 64)
f1
H
= t
When bit PWCR0 = 0, the conversion period is 16,384/ , so must be 2 MHz. In
this case t
When bit PWCR0 = 1, the conversion period is 32,768/ , so must be 4 MHz. In
this case t
Accordingly, for a conversion period of 8,192 µs, the system clock frequency ( )
must be 2 MHz or 4 MHz.
t
H1
f2
H1
Settings in order to obtain a conversion period of 8,192 µs:
= t
t
+ t
f1
f3
H2
..... = t
+ t
fn
fn
= 128 µs, with 1/ (resolution) = 0.5 µs.
= 128 µs, with 2/ (resolution) = 0.5 µs.
H3
Figure 11.2 PWM Output Waveform
t
+
H2
f64
..... t
t
f2
H64
1 conversion period
H
t
) corresponds to the data in PWDRU and PWDRL.
H3
t /2
t
H63
t
f63
4
/PWM is designated for PWM
t
H64
t
f64