HD64F3644H Renesas Electronics America, HD64F3644H Datasheet - Page 55

• Manufacturer Part Number: HD64F3644H
• Description: IC H8 MCU FLASH 32K 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644H

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Package: 64PQFP
• Family Name: H8
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 45
• Interface Type: SCI
• On-chip Adc: 8-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

2.5.2
Table 2.5 describes the arithmetic instructions.
Table 2.5
Instruction
ADD
SUB
ADDX
SUBX
INC
DEC
ADDS
SUBS
DAA
DAS
MULXU
DIVXU
CMP
NEG
Notes: * Size: Operand size
B: Byte
W: Word
Arithmetic Operations
Arithmetic Instructions
Size *
B/W
B
B
W
B
B
B
B/W
B
Function
Rd ± Rs
Performs addition or subtraction on data in two general registers, or
addition on immediate data and data in a general register. Immediate
data cannot be subtracted from data in a general register. Word data
can be added or subtracted only when both words are in general
registers.
Rd ± Rs ± C
Performs addition or subtraction with carry on data in two general
registers, or addition or subtraction with carry on immediate data and
data in a general register.
Rd ± 1
Increments or decrements a general register
Rd ± 1
Adds or subtracts 1 or 2 to or from a general register
Rd decimal adjust
Decimal-adjusts (adjusts to packed BCD) an addition or subtraction
result in a general register by referring to the CCR
Rd
Performs 8-bit
registers, providing a 16-bit result
Rd ÷ Rs
Performs 16-bit ÷ 8-bit unsigned division on data in two general
registers, providing an 8-bit quotient and 8-bit remainder
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and indicates the result in the CCR.
Word data can be compared only between two general registers.
0 – Rd
Obtains the two’s complement (arithmetic complement) of data in a
general register
Rs
Rd
Rd, Rd ± 2
Rd
Rd, Rd + #IMM
Rd
Rd
Rd, Rd ± #IMM ± C
8-bit unsigned multiplication on data in two general
Rd
Rd
Rev. 6.00 Sep 12, 2006 page 33 of 526
Rd
Rd
REJ09B0326-0600
Section 2 CPU