HD64F3644H Renesas Electronics America, HD64F3644H Datasheet - Page 70

• Manufacturer Part Number: HD64F3644H
• Description: IC H8 MCU FLASH 32K 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644H

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Package: 64PQFP
• Family Name: H8
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 45
• Interface Type: SCI
• On-chip Adc: 8-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 2 CPU
2.7.2
In the program execution state the CPU executes program instructions in sequence.
There are three modes in this state, two active modes (high speed and medium speed) and one
subactive mode. Operation is synchronized with the system clock in active mode (high speed and
medium speed), and with the subclock in subactive mode. See section 5, Power-Down Modes for
details on these modes.
2.7.3
In the program halt state there are five modes: two sleep modes (high speed and medium speed),
standby mode, watch mode, and subsleep mode. See section 5, Power-Down Modes for details on
these modes.
2.7.4
The exception-handling state is a transient state occurring when exception handling is started by a
reset or interrupt and the CPU changes its normal processing flow. In exception handling caused
by an interrupt, SP (R7) is referenced and the PC and CCR values are saved on the stack.
For details on interrupt handling, see section 3.3, Interrupts.
Rev. 6.00 Sep 12, 2006 page 48 of 526
REJ09B0326-0600
Program halt state
Program Execution State
Program Halt State
Exception-Handling State
Reset
occurs
Reset state
Reset
occurs
SLEEP instruction executed
Figure 2.15 State Transitions
Reset cleared
Reset occurs
Interrupt
source
Exception-handling state
Program execution state
Exception-
handling
request
Exception-
handling
complete