HD64F3644H Renesas Electronics America, HD64F3644H Datasheet - Page 87

• Manufacturer Part Number: HD64F3644H
• Description: IC H8 MCU FLASH 32K 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644H

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Package: 64PQFP
• Family Name: H8
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 45
• Interface Type: SCI
• On-chip Adc: 8-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit 6 INT
pin.
Bit 6: INTEG6
0
1
Bit 5 INT
pin.
Bit 5: INTEG5
0
1
Bits 4 to 0 INT
sensing of pins INT
Bit n: INTEGn
0
1
Interrupt Enable Register 1 (IENR1)
IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Upon reset, IENR1
is initialized to H'10.
Bit 7 Timer B1 Interrupt Enable (IENTB1): Bit 7 enables or disables timer B1 overflow
interrupt requests.
Bit 7: IENTB1
0
1
Bit
Initial value
Read/Write
6
5
Edge Select (INTEG6): Bit 6 selects the input sensing of the INT
Edge Select (INTEG5): Bit 5 selects the input sensing of the INT
4
IENTB1
to INT
4
R/W
Falling edge of INT
Rising edge of INT
Falling edge of INT
Rising edge of INT
Falling edge of INT
Rising edge of INT
Disables timer B1 interrupt requests
Enables timer B1 interrupt requests
Description
Description
Description
Description
to INT
7
0
0
Edge Select (INTEG4 to INTEG0): Bits 4 to 0 select the input
0
.
IENTA
R/W
0
6
6
5
n
6
5
n
and TMIB pin input is detected
and ADTRG pin input is detected
pin input is detected
and TMIB pin input is detected
and ADTRG pin input is detected
pin input is detected
0
5
4
1
Rev. 6.00 Sep 12, 2006 page 65 of 526
IEN3
R/W
3
0
Section 3 Exception Handling
IEN2
R/W
2
0
6
5
REJ09B0326-0600
pin and TMIB
pin and ADTRG
IEN1
R/W
1
0
(initial value)
(initial value)
(initial value)
(initial value)
(n = 4 to 0)
IEN0
R/W
0
0